XC161 Datasheet, PDF (17/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
The General Purpose Timer Units
The interrupts of GPT1 are controlled through the Interrupt Control Registers TxIC.
These registers are not part of the GPT1 block. The input and output lines of GPT1 are
connected to pins of ports P3 and P5. The control registers for the port functions are
located in the respective port modules.
Note: The timing requirements for external input signals can be found in Section 14.1.5,
Section 14.3 summarizes the module interface signals, including pins.
f _GPT
T2IN
T2EUD
T3IN
T3EUD
T4IN
T4EUD
2ⁿ: 1
T3CON.BPS1
Basic clock
T2
Mode
Control
Aux. Timer T2
U/D
Reload
Capture
T3
Mode
Control
Core Timer T3
U/D
Interrupt
Request
(T2IRQ)
Toggle Latch
T3OTL
Interrupt
Request
(T3IRQ)
T3OUT
T4
Mode
Control
Capture
Reload
Aux. Timer T4
U/D
Interrupt
Request
(T4IRQ)
mc_gpt0101_bldiax1.vsd
Figure 14-2 GPT1 Block Diagram (n = 2 … 5)
User’s Manual
GPT_X1, V2.0
14-3
V2.2, 2004-01