XC161 Datasheet, PDF (16/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
The General Purpose Timer Units
14.1
Timer Block GPT1
From a programmer’s point of view, the GPT1 block is composed of a set of SFRs as
summarized below. Those portions of port and direction registers which are used for
alternate functions by the GPT1 block are shaded.
Data Registers
T2
T3
T4
Control Registers
T2CON
T3CON
T4CON
SYSCON3
Interrupt Control
T2IC
T3IC
T4IC
Port Registers
ODP3
E
DP3
P3
ALTSEL0P3 E
P5
P5DIDIS
Tx
TxCON
TxIC
SYSCON3
G PT1 Tim er x Register
G PT1 Tim er x Control Register
G PT1 Tim er x Interrupt Ctrl. Reg.
System Ctrl. Reg. 3 (Per. M gm t.)
ODP3
Port 3 O pen Drain Control Register
DP3
Port 3 Direction Control Register
P3
Port 3 Data Register
ALTSEL0P3 Port 3 Alternate O utput Select Reg.
P5
Port 5 Data Register
P5DIDIS Port 5 Digital Input Disable Reg.
m c_gpt0100_registers.vsd
Figure 14-1 SFRs Associated with Timer Block GPT1
All three timers of block GPT1 (T2, T3, T4) can run in one of 4 basic modes: Timer Mode,
Gated Timer Mode, Counter Mode, or Incremental Interface Mode. All timers can count
up or down. Each timer of GPT1 is controlled by a separate control register TxCON.
Each timer has an input pin TxIN (alternate pin function) associated with it, which serves
as the gate control in gated timer mode, or as the count input in counter mode. The count
direction (up/down) may be programmed via software or may be dynamically altered by
a signal at the External Up/Down control input TxEUD (alternate pin function). An
overflow/underflow of core timer T3 is indicated by the Output Toggle Latch T3OTL,
whose state may be output on the associated pin T3OUT (alternate pin function). The
auxiliary timers T2 and T4 may additionally be concatenated with the core timer T3
(through T3OTL) or may be used as capture or reload registers for the core timer T3.
The current contents of each timer can be read or modified by the CPU by accessing the
corresponding timer count registers T2, T3, or T4, located in the non-bitaddressable SFR
space (see Section 14.1.6). When any of the timer registers is written to by the CPU in
the state immediately preceding a timer increment, decrement, reload, or capture
operation, the CPU write operation has priority in order to guarantee correct results.
User’s Manual
GPT_X1, V2.0
14-2
V2.2, 2004-01