XC161 Datasheet, PDF (369/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
Serial Data Link Module SDLM
Register INTCON contains all interrupt enable bits.
INTCON
Interrupt Control Register
15 14 13 12 11 10 9
0
r
Reset Value: 0000_H
876543210
ERR
IE
CRC
IE
ARL
IE
BRK
IE
END
F
IE
HD
IE
REC TRA
IE IE
rw rw rw rw rw rw rw rw
Field
Bits Type Description
TRAIE
0
rw Enable Transmit Interrupt
The transmission interrupt is disabled.
An interrupt is generated if bit MSGTRA is set.
RECIE
1
rw Enable Receive Interrupt
The receive interrupt is disabled.
An interrupt is generated if bit MSGREC is set.
HDIE
2
rw Enable Header Received Interrupt
The header interrupt is disabled.
An interrupt is generated if bit HEADER is set.
ENDFIE
3
rw Enable End of Frame Detection
The end-of-frame interrupt is disabled.
An interrupt is generated if bit ENDF is set.
BRKIE
4
rw Enable Break Received Interrupt
The break interrupt is disabled.
An interrupt is generated if bit BREAK is set.
ARLIE
5
rw Enable Arbitration Lost Interrupt
The arbitration-lost interrupt is disabled.
An interrupt is generated if bit ARL is set.
CRCIE
6
rw Enable CRC Error Interrupt
The CRC error interrupt is disabled.
An interrupt is generated if bit CRCER is set.
ERRIE
7
rw Enable Error Interrupt
The error interrupt is disabled.
An interrupt is generated if one of the bits SHORTH,
SHORTL or FORMAT is set.¹⁾
0
[15:8] –
Reserved; returns ‘0’ if read; should be written with ‘0’.
1) The COL flag does not generate an error interrupt!
User’s Manual
SDLM_X, V2.0
22-38
V2.2, 2004-01