XC161 Datasheet, PDF (213/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
High-Speed Synchronous Serial Interface (SSC)
Baudrate Timer/Reload Register
The SSC Baudrate Timer/Reload Register SSCx_BR has a double function.
While the SSC is disabled, it serves as the reload register for the baudrate timer. Writing
to it loads the timer reload register with the written reload value. Reading returns the
current reload value.
While the SSC is enabled, this register reflects the current baudrate timer contents.
Writing to this register is not allowed while the SSC is enabled.
Baudrate Calculation
The timer is loaded with the reload value and starts counting immediately when the SSC
is enabled. The formulas below calculate either the resulting baudrate for a given reload
value, or the required reload value for a given baudrate:
Baudrate = ---------------^f--^S---^S---^C----------------
2 × (<BR> + 1)
BG = -------------^f--^S---^S---^C-------------- – 1
2 × Baudrate
(19.1)
<BR> represents the contents of the reload register, taken as unsigned 16-bit integer;
while baudrate is equal to f_SCLK as shown in Figure 19-6.
The maximum baudrate that can be achieved when using a module clock of 40 MHz is
20 Mbit/s in Master Mode (with <BR> = 0000_H) or 10 Mbit/s in Slave Mode (with <BR> =
0001_H).
Table 19-1 lists some possible baudrates together with the required reload values and
the resulting bit times, assuming a module clock of 40 MHz.
Table 19-1 Typical Baudrates of the SSC (f_SSC = 40 MHz)
Reload Value
Baudrate (= f_SCLK)
0000_H
20 Mbit/s (only in Master Mode)
0001_H
10 Mbit/s
0009_H
2 Mbit/s
0013_H
1 Mbit/s
001A_H
750 kbit/s
0027_H
500 kbit/s
0063_H
200 kbit/s
00C7_H
100 kbit/s
FFFF_H
306.6 bit/s
Deviation
0.0%
0.0%
0.0%
0.0%
-1.25%
0.0%
0.0%
0.0%
0.0%
User’s Manual
SSC_X, V2.0
19-13
V2.2, 2004-01