XC161 Datasheet, PDF (336/419 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

22.2.1.2 J1850 Bits and Symbols
XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
Serial Data Link Module SDLM
Active
Data Bit `1'
Tv2
Passive
or
Tv1
Active
Data Bit `0'
Tv1
or
Tv2
Passive
Start of Frame ^Active
(SOF) _Passive
Tv3
End of Frame ^Active
(EOF) _Passive
Tv4
End of Data ^Active
(EOD) _Passive
Active
Normalization Bit
Passive
Tv3
Tv3
End of Last
Data Bit
Norm. Bit
Tv1 or Tv2
EOD
Start of
IFR Bit
Inter-Frame ^Active
Separation _Passive
Active
Break Signal
Passive
Tv6
Tv4
Tv3
Idle bus, may initiate
transmission at any time
End of Last
Data Bit
> Tv3
End of Last
Data Bit
EOD EOF
IFS _{May transmit if rising}
edge has been detected
after an EOF
Tv6
Tv4
EOF IFS
Figure 22-3 J1850 Variable Pulse Width (VPW) Format
Table 22-2 Timing Examples for VPW Format
Frequency
Tv1
Tv2
Tv3
Tv4
Tv5
Tv6
10.4 kbit/s
64 µs 128 µs 200 µs 280 µs –
–
User’s Manual
SDLM_X, V2.0
22-5
V2.2, 2004-01