LM3S9B81 Datasheet, PDF (98/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

System Control
6.2.1
6.2.2
6.2.2.1
■ Local control, such as reset (see “Reset Control” on page 98), power (see “Power
Control” on page 103) and clock control (see “Clock Control” on page 103)
■ System control (Run, Sleep, and Deep-Sleep modes), see “System Control” on page 110
Device Identification
Several read-only registers provide software with information on the microcontroller, such as version,
part number, SRAM size, Flash memory size, and other features. See the DID0 (page 114), DID1
(page 141), DC0-DC9 (page 143) and NVMSTAT (page 165) registers.
Reset Control
This section discusses aspects of hardware functions during reset as well as system software
requirements following the reset sequence.
Reset Sources
The LM3S9B81 microcontroller has six sources of reset:
1. Power-on reset (POR) (see page 99).
2. External reset input pin (RST) assertion (see page 99).
3. Internal brown-out (BOR) detector (see page 101).
4. Software-initiated reset (with the software reset registers) (see page 101).
5. A watchdog timer reset condition violation (see page 102).
6. MOSC failure (see page 102).
Table 6-3 provides a summary of results of the various reset operations.
Table 6-3. Reset Sources
Reset Source
Core Reset?
JTAG Reset?
On-Chip Peripherals Reset?
Power-On Reset
Yes
Yes
Yes
RST
Yes
Pin Config Only
Yes
Brown-Out Reset
Yes
No
Yes
Software System Request
Yes^a
No
Yes
Reset
Software Peripheral Reset
No
No
Yes^b
Watchdog Reset
Yes
No
Yes
MOSC Failure Reset
Yes
No
Yes
a. By using the SYSRESETREQ bit in the ARM Cortex-M3 Application Interrupt and Reset Control register
b. Programmable on a module-by-module basis using the Software Reset Control Registers.
After a reset, the Reset Cause (RESC) register is set with the reset cause. The bits in this register
are sticky and maintain their state across multiple reset sequences, except when an internal POR
is the cause, in which case, all the bits in the RESC register are cleared except for the POR indicator.
A bit in the RESC register can be cleared by writing a 0.
At any reset that resets the core, the user has the opportunity to direct the core to execute the ROM
Boot Loader or the application in Flash memory by using any GPIO signal in Ports A-H as configured
98
June 29, 2010
Texas Instruments-Advance Information