LM3S9B81 Datasheet, PDF (3/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

Stellaris® LM3S9B81 Microcontroller
Table of Contents
Revision History ............................................................................................................................. 35
About This Document .................................................................................................................... 40
Audience .............................................................................................................................................. 40
About This Manual ................................................................................................................................ 40
Related Documents ............................................................................................................................... 40
Documentation Conventions .................................................................................................................. 41
1
1.1
1.1.1
1.1.2
1.1.3
1.1.4
1.1.5
1.1.6
1.1.7
1.1.8
1.2
1.3
1.4
1.4.1
1.4.2
Architectural Overview .......................................................................................... 43
Functional Overview ...................................................................................................... 45
ARM Cortex™-M3 ......................................................................................................... 45
On-Chip Memory ........................................................................................................... 47
External Peripheral Interface ......................................................................................... 48
Serial Communications Peripherals ................................................................................ 49
System Integration ........................................................................................................ 55
Analog .......................................................................................................................... 60
JTAG and ARM Serial Wire Debug ................................................................................ 62
Packaging and Temperature .......................................................................................... 62
Target Applications ........................................................................................................ 62
High-Level Block Diagram ............................................................................................. 63
Additional Features ....................................................................................................... 65
Memory Map ................................................................................................................ 65
Hardware Details .......................................................................................................... 65
2
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
2.2.7
2.2.8
ARM Cortex-M3 Processor Core ........................................................................... 66
Block Diagram .............................................................................................................. 67
Functional Description ................................................................................................... 67
Programming Model ...................................................................................................... 67
Serial Wire and JTAG Debug ......................................................................................... 74
Embedded Trace Macrocell (ETM) ................................................................................. 74
Trace Port Interface Unit (TPIU) ..................................................................................... 74
ROM Table ................................................................................................................... 75
Memory Protection Unit (MPU) ....................................................................................... 75
Nested Vectored Interrupt Controller (NVIC) .................................................................... 75
System Timer (SysTick) ................................................................................................. 76
3
Memory Map ........................................................................................................... 79
4
Interrupts ................................................................................................................. 82
5
5.1
5.2
5.3
5.3.1
5.3.2
5.3.3
5.3.4
5.4
5.5
JTAG Interface ........................................................................................................ 85
Block Diagram .............................................................................................................. 86
Signal Description ......................................................................................................... 86
Functional Description ................................................................................................... 87
JTAG Interface Pins ...................................................................................................... 87
JTAG TAP Controller ..................................................................................................... 89
Shift Registers .............................................................................................................. 89
Operational Considerations ............................................................................................ 90
Initialization and Configuration ....................................................................................... 92
Register Descriptions .................................................................................................... 93
June 29, 2010
3
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