LM3S9B81 Datasheet, PDF (100/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

System Control
The external reset pin (RST) resets the microcontroller including the core and all the on-chip
peripherals except the JTAG TAP controller (see “JTAG Interface” on page 85). The external reset
sequence is as follows:
1. The external reset pin (RST) is asserted for the duration specified by T_MIN and then de-asserted
(see “Reset” on page 1088).
2. The internal reset is released and the core loads from memory the initial stack pointer, the initial
program counter, and the first instruction designated by the program counter, and then begins
execution.
To improve noise immunity and/or to delay reset at power up, the RST input may be connected to
an RC network as shown in Figure 6-2 on page 100.
Figure 6-2. External Circuitry to Extend Power-On Reset
VDD
Stellaris®
R_PU
RST
C₁
R_PU = 1 kΩ to 100 kΩ
C₁ = 1 nF to 10 µF
If the application requires the use of an external reset switch, Figure 6-3 on page 100 shows the
proper circuitry to use.
Figure 6-3. Reset Circuit Controlled by Switch
VDD
Stellaris®
R_PU
RST
R_S
C₁
Typical R_PU = 10 kΩ
Typical R_S = 470 Ω
C₁ = 10 nF
The R_PU and C₁ components define the power-on delay.
The external reset timing is shown in Figure 25-4 on page 1088.
100
June 29, 2010
Texas Instruments-Advance Information