LM3S9B81 Datasheet, PDF (574/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

Universal Asynchronous Receivers/Transmitters (UARTs)
14.1
– Receive single request asserted when data is in the FIFO; burst request asserted at
programmed FIFO level
– Transmit single request asserted when there is space in the FIFO; burst request asserted at
programmed FIFO level
Block Diagram
Figure 14-1. UART Module Block Diagram
System Clock
DMA Request
Interrupt
Identification
Registers
UARTPCellID0
UARTPCellID1
UARTPCellID2
UARTPCellID3
UARTPeriphID0
UARTPeriphID1
UARTPeriphID2
UARTPeriphID3
UARTPeriphID4
UARTPeriphID5
UARTPeriphID6
UARTPeriphID7
DMA Control
UARTDMACTL
Interrupt Control
UARTIFLS
UARTIM
UARTMIS
UARTRIS
UARTICR
UARTDR
Control/Status
UARTRSR/ECR
UARTFR
UARTLCRH
UARTCTL
UARTILPR
UARTLCTL
UARTLSS
UARTLTIM
TxFIFO
16 x 8
.
.
.
Baud Rate
Generator
UARTIBRD
UARTFBRD
RxFIFO
16 x 8
.
.
.
Transmitter
(with SIR
Transmit
Encoder)
Receiver
(with SIR
Receive
Decoder)
UnTx
UnRx
14.2
Signal Description
Table 14-1 on page 575 and Table 14-2 on page 575 list the external signals of the UART module
and describe the function of each. The UART signals are alternate functions for some GPIO signals
and default to be GPIO signals at reset, with the exception of the U0Rx and U0Tx pins which default
to the UART function. The column in the table below titled "Pin Mux/Pin Assignment" lists the possible
GPIO pin placements for these UART signals. The AFSEL bit in the GPIO Alternate Function
Select (GPIOAFSEL) register (page 318) should be set to choose the UART function. The number
in parentheses is the encoding that must be programmed into the PMCn field in the GPIO Port
Control (GPIOPCTL) register (page 336) to assign the UART signal to the specified GPIO port pin.
For more information on configuring GPIOs, see “General-Purpose Input/Outputs
(GPIOs)” on page 294.
574
June 29, 2010
Texas Instruments-Advance Information