LM3S9B81 Datasheet, PDF (698/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

Inter-Integrated Circuit (I²C) Interface
Table 16-5. Write Field Decoding for I2CMCS[3:0] Field (continued)
Current I2CMSA[0]
State
R/S
ACK
I2CMCS[3:0]
STOP START
Description
RUN
Master
X
Receive
X
0
0
0
1 RECEIVE operation with negative ACK (master remains
in Master Receive state).
X
1
0
0 STOP condition (master goes to Idle state).^b
X
0
1
0
1 RECEIVE followed by STOP condition (master goes to
Idle state).
X
1
0
0
1 RECEIVE operation (master remains in Master Receive
state).
X
1
1
0
1 Illegal.
1
0
0
1
1 Repeated START condition followed by RECEIVE
operation with a negative ACK (master remains in Master
Receive state).
1
0
1
1
1 Repeated START condition followed by RECEIVE and
STOP condition (master goes to Idle state).
1
1
0
1
1 Repeated START condition followed by RECEIVE
(master remains in Master Receive state).
0
X
0
1
1 Repeated START condition followed by TRANSMIT
(master goes to Master Transmit state).
0
X
1
1
1 Repeated START condition followed by TRANSMIT and
STOP condition (master goes to Idle state).
All other combinations not listed are non-operations. NOP.
a. An X in a table cell indicates the bit can be 0 or 1.
b. In Master Receive mode, a STOP condition should be generated only after a Data Negative Acknowledge executed by
the master or an Address Negative Acknowledge executed by the slave.
698
June 29, 2010
Texas Instruments-Advance Information