LM3S9B81 Datasheet, PDF (356/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

External Peripheral Interface (EPI)
10.3.2
10.4
value = EPIREADFIFO; // drain
The above algorithm can be optimized in code; however, the important point is to wait for the cancel
to complete because the external interface could have been in the process of reading a value when
the cancel came in, and it must be allowed to complete.
DMA Operation
The µDMA can be used to efficiently transfer data from and to the NBRFIFO and the WFIFO. The
µDMA has one channel for write and one for read. The write channel copies values to the WFIFO
when the WFIFO is at the level specified by the EPI FIFO Level Selects (EPIFIFOLVL) register.
The non-blocking read channel copies values from the NBRFIFO when the NBRFIFO is at the level
specified by the EPIFIFOLVL register. For non-blocking reads, the start address, the size per
transaction, and the count of elements must be programmed in the µDMA. Note that both non-blocking
read register sets can be used, and they fill the NBRFIFO such that one runs to completion, then
the next one starts (they do not interleave).
For blocking reads, the µDMA software channel (or another unused channel) is used for
memory-to-memory transfers (or memory to peripheral, where some other peripheral is used). In
this situation, the µDMA stalls until the read is complete and is not able to service another channel
until the read is done. As a result, the arbitration size should normally be programmed to one access
at a time. The µDMA controller can also transfer from and to the NBRFIFO and the WFIFO using
the µDMA software channel in memory mode, however, the µDMA is stalled once the NBRFIFO is
empty or the WFIFO is full. Note that when the µDMA controller is stalled, the core continues
operation. See “Micro Direct Memory Access (μDMA)” on page 236 for more information on configuring
the µDMA.
Initialization and Configuration
To enable and initialize the EPI controller, the following steps are necessary:
1. Enable the EPI module using the RCGC1 register. See page 174.
2. Enable the clock to the appropriate GPIO module via the RCGC2 register. See page 183. To
find out which GPIO port to enable, refer to Table 10-1 on page 352 or Table 10-2 on page 353.
3. Set the GPIO AFSEL bits for the appropriate pins. See page 318. To determine which GPIOs to
configure, see Table 23-4 on page 1036.
4. Configure the GPIO current level and/or slew rate as specified for the mode selected. See
page 320 and page 328.
5. Configure the PMCn fields in the GPIOPCTL register to assign the EPI signals to the appropriate
pins. See page 336 and Table 23-5 on page 1043.
6. Select the mode for the EPI block to SDRAM, HB8, HB16, or general parallel use, using the
MODE field in the EPI Configuration (EPICFG) register. Set the mode-specific details (if needed)
using the appropriate mode configuration EPI xxx Configuration (EPIxxxCFG) and EPI xxx
Configuration 2 (EPIxxxCFG2) registers. Set the EPI Main Baud Rate (EPIBAUD) register if
the baud rate must be slower than the system clock rate.
7. Configure the address mapping using the EPI Address Map (EPIADDRMAP) register. The
selected start address and range is dependent on the type of external device and maximum
address (as appropriate). For example, for a 512-megabit SDRAM, program the ERADR field to
0x1 for address 0x6000.0000 or 0x2 for address 0x8000.0000; and program the ERSZ field to
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June 29, 2010
Texas Instruments-Advance Information