LM3S9B81 Datasheet, PDF (113/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

Stellaris® LM3S9B81 Microcontroller
Table 6-8. System Control Register Map (continued)
Offset Name
Type
Reset
Description
0x064 PLLCFG
0x06C GPIOHBCTL
0x070 RCC2
0x07C MOSCCTL
0x100 RCGC0
0x104 RCGC1
0x108 RCGC2
0x110 SCGC0
0x114 SCGC1
0x118 SCGC2
0x120 DCGC0
0x124 DCGC1
0x128 DCGC2
0x144 DSLPCLKCFG
0x150 PIOSCCAL
0x170 I2SMCLKCFG
0x190 DC9
0x1A0 NVMSTAT
RO
-
XTAL to PLL Translation
R/W
0x0000.0000 GPIO High-Performance Bus Control
R/W
0x07C0.6810 Run-Mode Clock Configuration 2
R/W
0x0000.0000 Main Oscillator Control
R/W
0x00000040 Run Mode Clock Gating Control Register 0
R/W
0x00000000 Run Mode Clock Gating Control Register 1
R/W
0x00000000 Run Mode Clock Gating Control Register 2
R/W
0x00000040 Sleep Mode Clock Gating Control Register 0
R/W
0x00000000 Sleep Mode Clock Gating Control Register 1
R/W
0x00000000 Sleep Mode Clock Gating Control Register 2
R/W
0x00000040 Deep Sleep Mode Clock Gating Control Register 0
R/W
0x00000000 Deep-Sleep Mode Clock Gating Control Register 1
R/W
0x00000000 Deep Sleep Mode Clock Gating Control Register 2
R/W
0x0780.0000 Deep Sleep Clock Configuration
R/W
0x0000.0000 Precision Internal Oscillator Calibration
R/W
0x0000.0000 I2S MCLK Configuration
RO
0x00FF.00FF Device Capabilities 9 ADC Digital Comparators
RO
0x0000.0001 Non-Volatile Memory Information
6.5 Register Descriptions
All addresses given are relative to the System Control base address of 0x400F.E000.
See
page
129
130
132
135
166
174
183
169
177
186
172
180
189
136
138
139
163
165
June 29, 2010
113
Texas Instruments-Advance Information