LM3S9B81 Datasheet, PDF (813/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

Stellaris® LM3S9B81 Microcontroller
19.3.4
19.3.5
logic is used to detect the presence of valid energy from 100BASE-T, 10BASE-T, or auto-negotiation
signals. While the PHY is powered down, nothing is transmitted. When link pulses or packets are
received, the PHY powers-up. The PHY automatically resets itself into the state it had prior to power
down and sets the EONIS bit in the MR29 register. The first and possibly the second packet to
activate the ENERGYON mode may be lost.
Interrupts
The Ethernet Controller can generate an interrupt for one or more of the following conditions:
■ A frame has been received into an empty RX FIFO
■ A frame transmission error has occurred
■ A frame has been transmitted successfully
■ A frame has been received with inadequate room in the RX FIFO (overrun)
■ A frame has been received with one or more error conditions (for example, FCS failed)
■ An MII management transaction between the MAC and PHY layers has completed
■ One or more of the following PHY layer conditions occurs:
– Auto-Negotiate Complete
– Remote Fault
– Link Partner Acknowledge
– Parallel Detect Fault
– Page Received
Refer to Ethernet PHY Management Register 29 - Interrupt Source Flags (MR29) (see
page 858) for additional details regarding PHY interrupts.
DMA Operation
The Ethernet peripheral provides request signals to the μDMA controller and has a dedicated channel
for transmit and one for receive. The request is a single type for both channels. Burst requests are
not supported. The RX channel request is asserted when a packet is received while the TX channel
request is asserted when the transmit FIFO becomes empty.
No special configuration is needed to enable the Ethernet peripheral for use with the μDMA controller.
Because the size of a received packet is not known until the header is examined, it is best to set
up the initial μDMA transfer to copy the first 4 words including the packet length plus the Ethernet
header from the RX FIFO when the RX request occurs. The μDMA causes an interrupt when this
transfer is complete. Upon entering the interrupt handler, the packet length in the FIFO and the
Ethernet header are in a buffer and can be examined. Once the packet length is known, then another
μDMA transfer can be set up to transfer the remaining received packet payload from the FIFO into
a buffer. This transfer should be initiated by software. Another interrupt occurs when this transfer
is done.
Even though the TX channel generates a TX empty request, the recommended way to handle μDMA
transfers for transmitting packets is to set up the transfer from the buffer containing the packet to
June 29, 2010
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