LM3S9B81 Datasheet, PDF (386/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

External Peripheral Interface (EPI)
Register 4: EPI Host-Bus 8 Configuration (EPIHB8CFG), offset 0x010
Important: The MODE field in the EPICFG register determines which configuration register is
accessed for offsets 0x010 and 0x014.
To access EPIHB8CFG, the MODE field must be 0x2.
The Host Bus 8 Configuration register is activated when the HB8 mode is selected. The HB8 mode
supports muxed address/data (overlay of lower 8 address and all 8 data pins), separated
address/data, and address-less FIFO mode. Note that this register is reset when the MODE field in
the EPICFG register is changed. If another mode is selected and the HB8 mode is selected again,
the values must be reinitialized.
This mode is intended to support SRAMs, Flash memory (read), FIFOs, CPLDs/FPGAs, and devices
with an MCU/HostBus slave or 8-bit FIFO interface support.
Refer to Table 10-5 on page 363 for information on signal configuration controlled by this register
and the EPIHB8CFG2 register.
If less address pins are required, the corresponding AFSEL bit (page 318) should not be enabled so
the EPI controller does not drive those pins, and they are available as standard GPIOs.
There is no direct chip enable (CE) model. Instead, CE can be handled in one of three ways:
1. Manually control via GPIOs.
2. Associate one or more upper address pins to CE. Because CE is normally CEn, lower addresses
are not used. For example, if pins EPI0S27 and EPI0S26 are used for Device 1 and 0
respectively, then address 0x6800.0000 accesses Device 0 (Device 1 has its CEn high), and
0x6400.0000 accesses Device 1 (Device 0 has its CEn high). The pull-up behavior on the
corresponding GPIOs must be properly configured to ensure that the pins are disabled when
the interface is not in use.
3. With certain SRAMs, the ALE can be used as CEn because the address remains stable after
the ALE strobe. The subsequent WRn or RDn signals write or read when ALE is low thus
providing CEn functionality.
EPI Host-Bus 8 Configuration (EPIHB8CFG)
Base 0x400D.0000
Offset 0x010
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
XFFEN XFEEN WRHIGH RDHIGH
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
R/W
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
MAXWAIT
WRWS
RDWS
Type R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
3
2
reserved
RO
RO
0
0
1
0
MODE
R/W
R/W
0
0
Bit/Field
31:24
Name
reserved
Type
RO
Reset
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
386
June 29, 2010
Texas Instruments-Advance Information