LM3S9B81 Datasheet, PDF (744/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

Inter-Integrated Circuit Sound (I²S) Interface
Register 14: I²S Interrupt Mask (I2SIM), offset 0xC10
This register masks the interrupts to the CPU.
I2S Interrupt Mask (I2SIM)
Base 0x4005.4000
Offset 0xC10
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
RXREIM RXSRIM
reserved
TXWEIM TXSRIM
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
RO
RO
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:6
5
Name
reserved
RXREIM
Type
RO
R/W
Reset Description
0x0000.00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
Receive FIFO Read Error
Value Description
0 The receive FIFO read error interrupt is masked and not sent
to the CPU.
1 The receive FIFO read error is enabled to be sent to the interrupt
controller.
4
RXSRIM
R/W
0
Receive FIFO Service Request
Value Description
0 The receive FIFO service request interrupt is masked and not
sent to the CPU.
1 The receive FIFO service request is enabled to be sent to the
interrupt controller.
3:2
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
TXWEIM
R/W
0
Transmit FIFO Write Error
Value Description
0 The transmit FIFO write error interrupt is masked and not sent
to the CPU.
1 The transmit FIFO write error is enabled to be sent to the
interrupt controller.
744
June 29, 2010
Texas Instruments-Advance Information