LM3S9B81 Datasheet, PDF (72/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

ARM Cortex-M3 Processor Core
Table 2-2. 32-Bit Cortex-M3 Instruction Set Summary (continued)
Operation
Assembler
Memory doubleword from register address 8-bit offset 4, postindexed
LDRD.W <Rxf>, <Rxf2>, [<Rn>], #+/–<offset_8> * 4
Load register exclusive calculates an address from a base register value and LDREX<c> <Rt>,[<Rn>{,#<imm>}]
an immediate offset, loads a word from memory, writes it to a register
Load register exclusive halfword calculates an address from a base register LDREXH<c> <Rt>,[<Rn>{,#<imm>}]
value and an immediate offset, loads a halfword from memory, writes it to a
register
Load register exclusive byte calculates an address from a base register value LDREXB<c> <Rt>,[<Rn>{,#<imm>}]
and an immediate offset, loads a byte from memory, writes it to a register
Memory halfword [15:0] from base register address + immediate 12-bit offset LDRH.W <Rxf>, [<Rn>, #<offset_12>]
Memory halfword [15:0] from base register address immediate 8-bit offset, LDRH.W <Rxf>, [<Rn>, #<+/–<offset_8>]!
preindexed
Memory halfword [15:0] from base register address immediate 8-bit offset, LDRH.W <Rxf>. [<Rn>], #+/-<offset_8>
postindexed
Memory halfword [15:0] from register address shifted left by 0, 1, 2, or 3 places LDRH.W <Rxf>, [<Rn>, <Rm>{, LSL #<shift>}]
Memory halfword from PC address immediate 12-bit offset
LDRH.W <Rxf>, [PC, #+/–<offset_12>]
Memory signed byte [7:0] from base register address + immediate 12-bit offset LDRSB.W <Rxf>, [<Rn>, #<offset_12>]
Memory signed byte [7:0] from base register address immediate 8-bit offset, LDRSB.W <Rxf>. [<Rn>], #+/-<offset_8>
postindexed
Memory signed byte [7:0] from base register address immediate 8-bit offset, LDRSB.W <Rxf>, [<Rn>, #<+/–<offset_8>]!
preindexed
Memory signed byte [7:0] from register address shifted left by 0, 1, 2, or 3 LDRSB.W <Rxf>, [<Rn>, <Rm>{, LSL #<shift>}]
places
Memory signed byte from PC address immediate 12-bit offset
LDRSB.W <Rxf>, [PC, #+/–<offset_12>]
Memory signed halfword [15:0] from base register address + immediate 12-bit LDRSH.W <Rxf>, [<Rn>, #<offset_12>]
offset
Memory signed halfword [15:0] from base register address immediate 8-bit LDRSH.W <Rxf>. [<Rn>], #+/-<offset_8>
offset, postindexed
Memory signed halfword [15:0] from base register address immediate 8-bit LDRSH.W <Rxf>, [<Rn>, #<+/–<offset_8>]!
offset, preindexed
Memory signed halfword [15:0] from register address shifted left by 0, 1, 2, LDRSH.W <Rxf>, [<Rn>, <Rm>{, LSL #<shift>}]
or 3 places
Memory signed halfword from PC address immediate 12-bit offset
LDRSH.W <Rxf>, [PC, #+/–<offset_12>]
Logical shift left register value by number in register
LSL{S}.W <Rd>, <Rn>, <Rm>
Logical shift right register value by number in register
LSR{S}.W <Rd>, <Rn>, <Rm>
Multiply two signed or unsigned register values and add the low 32 bits to a MLA.W <Rd>, <Rn>, <Rm>, <Racc>
register value
Multiply two signed or unsigned register values and subtract the low 32 bits MLS.W <Rd>, <Rn>, <Rm>, <Racc>
from a register value
Move immediate 12-bit value to register
MOV{S}.W <Rd>, #<modify_constant(immed_12)>
Move shifted register value to register
MOV{S}.W <Rd>, <Rm>{, <shift>}
Move immediate 16-bit value to top halfword [31:16] of register
MOVT.W <Rd>, #<immed_16>
Move immediate 16-bit value to bottom halfword [15:0] of register and clear MOVW.W <Rd>, #<immed_16>
top halfword [31:16]
Move to register from status
MRS<c> <Rd>, <psr>
Move to status register
MSR<c> <psr>_<fields>,<Rn>
Multiply two signed or unsigned register values
MUL.W <Rd>, <Rn>, <Rm>
No operation
NOP.W
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June 29, 2010
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