LM3S9B81 Datasheet, PDF (20/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

Table of Contents
Register 28: DMA PrimeCell Identification 1 (DMAPCellID1), offset 0xFF4 ........................................... 291
Register 29: DMA PrimeCell Identification 2 (DMAPCellID2), offset 0xFF8 ........................................... 292
Register 30: DMA PrimeCell Identification 3 (DMAPCellID3), offset 0xFFC ........................................... 293
General-Purpose Input/Outputs (GPIOs) ................................................................................... 294
Register 1: GPIO Data (GPIODATA), offset 0x000 ............................................................................ 308
Register 2: GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 309
Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 310
Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 311
Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 312
Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 313
Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 314
Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 315
Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 317
Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 318
Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 320
Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 321
Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 322
Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 323
Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 324
Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 326
Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 328
Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 329
Register 19: GPIO Lock (GPIOLOCK), offset 0x520 ............................................................................ 331
Register 20: GPIO Commit (GPIOCR), offset 0x524 ............................................................................ 332
Register 21: GPIO Analog Mode Select (GPIOAMSEL), offset 0x528 ................................................... 334
Register 22: GPIO Port Control (GPIOPCTL), offset 0x52C ................................................................. 336
Register 23: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 338
Register 24: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 339
Register 25: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 340
Register 26: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 341
Register 27: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 342
Register 28: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 ....................................... 343
Register 29: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 344
Register 30: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 345
Register 31: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 346
Register 32: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 347
Register 33: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 348
Register 34: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 349
External Peripheral Interface (EPI) ............................................................................................. 350
Register 1: EPI Configuration (EPICFG), offset 0x000 ....................................................................... 380
Register 2: EPI Main Baud Rate (EPIBAUD), offset 0x004 ................................................................. 382
Register 3: EPI SDRAM Configuration (EPISDRAMCFG), offset 0x010 .............................................. 384
Register 4: EPI Host-Bus 8 Configuration (EPIHB8CFG), offset 0x010 ............................................... 386
Register 5: EPI Host-Bus 16 Configuration (EPIHB16CFG), offset 0x010 ........................................... 390
Register 6: EPI General-Purpose Configuration (EPIGPCFG), offset 0x010 ........................................ 394
Register 7: EPI Host-Bus 8 Configuration 2 (EPIHB8CFG2), offset 0x014 .......................................... 399
Register 8: EPI Host-Bus 16 Configuration 2 (EPIHB16CFG2), offset 0x014 ....................................... 401
Register 9: EPI General-Purpose Configuration 2 (EPIGPCFG2), offset 0x014 ................................... 403
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June 29, 2010
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