LM3S9B81 Datasheet, PDF (68/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

ARM Cortex-M3 Processor Core
Thread mode is privileged out of reset, but you can change it to user or unprivileged by setting
the CONTROL[0] bit using the MSR instruction. User access prevents:
– Use of some instructions such as CPS to set FAULTMASK and PRIMASK
– Access to most registers in System Control Space (SCS)
When Thread mode has been changed from privileged to user, it cannot change itself back to
privileged. Only a Handler can change the privilege of Thread mode. Handler mode is always
privileged.
■ Register set - The processor has the following 32-bit registers:
– 13 general-purpose registers, r0-r12
– Stack point alias of banked registers, SP_process and SP_main
– Link register, r14
– Program counter, r15
– One program status register, xPSR.
■ Data types - The processor supports the following data types:
– 32-bit words
– 16-bit halfwords
– 8-bit bytes
■ Memory formats - The processor views memory as a linear collection of bytes numbered in
ascending order from 0. For example, bytes 0-3 hold the first stored word and bytes 4-7 hold the
second stored word. The processor accesses code and data in little-endian format, which means
that the byte with the lowest address in a word is the least-significant byte of the word. The byte
with the highest address in a word is the most significant. The byte at address 0 of the memory
system connects to data lines 7-0.
■ Instruction set - The Cortex-M3 instruction set contains both 16 and 32-bit instructions. These
instructions are summarized in Table 2-1 on page 68 and Table 2-2 on page 70, respectively.
Table 2-1. 16-Bit Cortex-M3 Instruction Set Summary
Operation
Add register value and C flag to register value
Add immediate 3-bit value to register
Add immediate 8-bit value to register
Add low register value to low register value
Add high register value to low or high register value
Add 4* (immediate 8-bit value) with PC to register
Add 4* (immediate 8-bit value) with SP to register
Add 4* (immediate 7-bit value) to SP
Bitwise AND register values
Arithmetic shift right by immediate number
Assembler
ADC <Rd>, <Rm>
ADD <Rd>, <Rn>, #<immed_3>
ADD <Rd>, #<immed_8>
ADD <Rd>, <Rn>, <Rm>
ADD <Rd>, <Rm>
ADD <Rd>, PC, #<immed_8> * 4
ADD <Rd>, SP, #<immed_8> * 4
ADD SP, #<immed_7> * 4
AND <Rd>, <Rm>
ASR <Rd>, <Rm>, #<immed_5>
68
June 29, 2010
Texas Instruments-Advance Information