LM3S9B81 Datasheet, PDF (219/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

Stellaris® LM3S9B81 Microcontroller
Register 11: ROM Control (RMCTL), offset 0x0F0
This register provides control of the ROM controller state. This register offset is relative to the System
Control base address of 0x400F.E000.
ROM Control (RMCTL)
Base 0x400F.E000
Offset 0x0F0
Type R/W1C, reset -
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
BA
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO R/W1C
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
Bit/Field
31:1
0
Name
reserved
BA
Type
Reset Description
RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W1C
-
Boot Alias
At reset, the user has the opportunity to direct the core to execute the
ROM Boot Loader or the application in Flash memory by using any
GPIO signal as configured in the BOOTCFG register. If the ROM boot
loader is not selected, the system control module checks address
0x000.0004 to see if the Flash memory has a valid reset vector. If the
data at address 0x0000.0004 is 0xFFFF.FFFF, then it is assumed that
the Flash memory has not yet been programmed, and this bit is then
set by hardware so that the on-chip ROM appears at address 0x0.
Value Description
1 The microcontroller's ROM appears at address 0x0. This bit is
set automatically if the data at address 0x0000.0004 is
0xFFFF.FFFF.
0 The Flash memory is at address 0x0.
This bit is cleared by writing a 1 to this bit position.
June 29, 2010
219
Texas Instruments-Advance Information