LM3S9B81 Datasheet, PDF (21/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

Stellaris® LM3S9B81 Microcontroller
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
Register 31:
Register 32:
EPI Address Map (EPIADDRMAP), offset 0x01C ............................................................. 404
EPI Read Size 0 (EPIRSIZE0), offset 0x020 .................................................................... 406
EPI Read Size 1 (EPIRSIZE1), offset 0x030 .................................................................... 406
EPI Read Address 0 (EPIRADDR0), offset 0x024 ............................................................ 407
EPI Read Address 1 (EPIRADDR1), offset 0x034 ............................................................ 407
EPI Non-Blocking Read Data 0 (EPIRPSTD0), offset 0x028 ............................................. 408
EPI Non-Blocking Read Data 1 (EPIRPSTD1), offset 0x038 ............................................. 408
EPI Status (EPISTAT), offset 0x060 ................................................................................ 410
EPI Read FIFO Count (EPIRFIFOCNT), offset 0x06C ...................................................... 412
EPI Read FIFO (EPIREADFIFO), offset 0x070 ................................................................ 413
EPI Read FIFO Alias 1 (EPIREADFIFO1), offset 0x074 .................................................... 413
EPI Read FIFO Alias 2 (EPIREADFIFO2), offset 0x078 .................................................... 413
EPI Read FIFO Alias 3 (EPIREADFIFO3), offset 0x07C ................................................... 413
EPI Read FIFO Alias 4 (EPIREADFIFO4), offset 0x080 .................................................... 413
EPI Read FIFO Alias 5 (EPIREADFIFO5), offset 0x084 .................................................... 413
EPI Read FIFO Alias 6 (EPIREADFIFO6), offset 0x088 .................................................... 413
EPI Read FIFO Alias 7 (EPIREADFIFO7), offset 0x08C ................................................... 413
EPI FIFO Level Selects (EPIFIFOLVL), offset 0x200 ........................................................ 414
EPI Write FIFO Count (EPIWFIFOCNT), offset 0x204 ...................................................... 416
EPI Interrupt Mask (EPIIM), offset 0x210 ......................................................................... 417
EPI Raw Interrupt Status (EPIRIS), offset 0x214 .............................................................. 418
EPI Masked Interrupt Status (EPIMIS), offset 0x218 ........................................................ 420
EPI Error Interrupt Status and Clear (EPIEISC), offset 0x21C ........................................... 421
General-Purpose Timers ............................................................................................................. 423
Register 1: GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. 440
Register 2: GPTM Timer A Mode (GPTMTAMR), offset 0x004 ........................................................... 441
Register 3: GPTM Timer B Mode (GPTMTBMR), offset 0x008 ........................................................... 443
Register 4: GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 445
Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 448
Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 450
Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 453
Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 456
Register 9: GPTM Timer A Interval Load (GPTMTAILR), offset 0x028 ................................................ 458
Register 10: GPTM Timer B Interval Load (GPTMTBILR), offset 0x02C ................................................ 459
Register 11: GPTM Timer A Match (GPTMTAMATCHR), offset 0x030 .................................................. 460
Register 12: GPTM Timer B Match (GPTMTBMATCHR), offset 0x034 ................................................. 461
Register 13: GPTM Timer A Prescale (GPTMTAPR), offset 0x038 ....................................................... 462
Register 14: GPTM Timer B Prescale (GPTMTBPR), offset 0x03C ...................................................... 463
Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 464
Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 465
Register 17: GPTM Timer A (GPTMTAR), offset 0x048 ....................................................................... 466
Register 18: GPTM Timer B (GPTMTBR), offset 0x04C ....................................................................... 467
Register 19: GPTM Timer A Value (GPTMTAV), offset 0x050 ............................................................... 469
Register 20: GPTM Timer B Value (GPTMTBV), offset 0x054 .............................................................. 470
Watchdog Timers ......................................................................................................................... 471
Register 1: Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 475
Register 2: Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 476
Register 3: Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 477
June 29, 2010
21
Texas Instruments-Advance Information