LM3S9B81 Datasheet, PDF (746/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

Inter-Integrated Circuit Sound (I²S) Interface
Register 15: I²S Raw Interrupt Status (I2SRIS), offset 0xC14
This register reads the unmasked interrupt status.
I2S Raw Interrupt Status (I2SRIS)
Base 0x4005.4000
Offset 0xC14
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
RXRERIS RXSRRIS
reserved
TXWERIS TXSRRIS
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:6
5
4
3:2
1
Name
reserved
RXRERIS
RXSRRIS
reserved
TXWERIS
Type
RO
RO
RO
RO
RO
Reset Description
0x0000.00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
Receive FIFO Read Error
Value Description
1 A receive FIFO read error interrupt has occurred.
0 No interrupt
This bit is cleared by setting the RXREIC bit in the I2SIC register.
0
Receive FIFO Service Request
Value Description
1 A receive FIFO service request interrupt has occurred.
0 No interrupt
This bit is cleared when the level in the receive FIFO has risen to a value
greater than the value programmed in the LIMIT field in the I2SRXLIMIT
register.
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
Transmit FIFO Write Error
Value Description
1 A transmit FIFO write error interrupt has occurred.
0 No interrupt
This bit is cleared by setting the TXWEIC bit in the I2SIC register.
746
June 29, 2010
Texas Instruments-Advance Information