LM3S9B81 Datasheet, PDF (648/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

Synchronous Serial Interface (SSI)
■ Master operation
■ Freescale SPI mode (SPO=1, SPH=1)
■ 1 Mbps bit rate
■ 8 data bits
Assuming the system clock is 20 MHz, the bit rate calculation would be:
SSIClk = SysClk / (CPSDVSR * (1 + SCR)) 1x106 = 20x106 / (CPSDVSR * (1 +
SCR))
In this case, if CPSDVSR=0x2, SCR must be 0x9.
The configuration sequence would be as follows:
1. Ensure that the SSE bit in the SSICR1 register is clear.
2. Write the SSICR1 register with a value of 0x0000.0000.
3. Write the SSICPSR register with a value of 0x0000.0002.
4. Write the SSICR0 register with a value of 0x0000.09C7.
5. The SSI is then enabled by setting the SSE bit in the SSICR1 register.
15.5
Register Map
Table 15-3 on page 648 lists the SSI registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that SSI module’s base address:
■ SSI0: 0x4000.8000
■ SSI1: 0x4000.9000
Note that the SSI module clock must be enabled before the registers can be programmed (see
page 174).
Note: The SSI must be disabled (see the SSE bit in the SSICR1 register) before any of the control
registers are reprogrammed.
Table 15-3. SSI Register Map
Offset Name
Type
0x000 SSICR0
R/W
0x004 SSICR1
R/W
0x008 SSIDR
R/W
0x00C SSISR
RO
0x010 SSICPSR
R/W
0x014 SSIIM
R/W
0x018 SSIRIS
RO
Reset
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0003
0x0000.0000
0x0000.0000
0x0000.0008
Description
SSI Control 0
SSI Control 1
SSI Data
SSI Status
SSI Clock Prescale
SSI Interrupt Mask
SSI Raw Interrupt Status
See
page
650
652
654
655
657
658
659
648
June 29, 2010
Texas Instruments-Advance Information