LM3S9B81 Datasheet, PDF (716/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

Inter-Integrated Circuit Sound (I²S) Interface
Table 17-1. Signals for I2S (100LQFP)
Pin Name
I2S0RXMCLK
I2S0RXSCK
I2S0RXSD
I2S0RXWS
I2S0TXMCLK
I2S0TXSCK
I2S0TXSD
I2S0TXWS
Pin Number Pin Mux / Pin
Assignment
29
PA3 (9)
98
PD5 (8)
10
PD0 (8)
28
PA2 (9)
97
PD4 (8)
11
PD1 (8)
61
PF1 (8)
30
PA4 (9)
90
PB6 (9)
99
PD6 (8)
5
PE5 (9)
47
PF0 (8)
6
PE4 (9)
31
PA5 (9)
100
PD7 (8)
Pin Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Buffer Type^a Description
TTL
I²S module 0 receive master clock.
TTL
I²S module 0 receive clock.
TTL
I²S module 0 receive data.
TTL
I²S module 0 receive word select.
TTL
I²S module 0 transmit master clock.
TTL
I²S module 0 transmit clock.
TTL
I²S module 0 transmit data.
TTL
I²S module 0 transmit word select.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
Table 17-2. Signals for I2S (108BGA)
Pin Name
I2S0RXMCLK
I2S0RXSCK
I2S0RXSD
I2S0RXWS
I2S0TXMCLK
I2S0TXSCK
I2S0TXSD
I2S0TXWS
Pin Number Pin Mux / Pin
Assignment
L4
PA3 (9)
C6
PD5 (8)
G1
PD0 (8)
M4
PA2 (9)
B5
PD4 (8)
G2
PD1 (8)
H12
PF1 (8)
L5
PA4 (9)
A7
PB6 (9)
A3
PD6 (8)
B3
PE5 (9)
M9
PF0 (8)
B2
PE4 (9)
M5
PA5 (9)
A2
PD7 (8)
Pin Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Buffer Type^a Description
TTL
I²S module 0 receive master clock.
TTL
I²S module 0 receive clock.
TTL
I²S module 0 receive data.
TTL
I²S module 0 receive word select.
TTL
I²S module 0 transmit master clock.
TTL
I²S module 0 transmit clock.
TTL
I²S module 0 transmit data.
TTL
I²S module 0 transmit word select.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
17.3
Functional Description
The Inter-Integrated Circuit Sound (I²S) module contains separate transmit and receive engines.
Each engine consists of the following:
■ Serial encoder for the transmitter; serial decoder for the receiver
■ 8-entry FIFO to store sample data
■ Independent configuration of all programmable settings
716
June 29, 2010
Texas Instruments-Advance Information