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LM3S9B81 Datasheet, PDF (351/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller | |||
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Stellaris® LM3S9B81 Microcontroller
10.1
â Support of both muxed and de-muxed address and data
â Access to a range of devices supporting the non-address FIFO x8 and x16 interface variant,
with support for external FIFO (XFIFO) EMPTY and FULL signals
â Speed controlled, with read and write data wait-state counters
â Chip select modes include ALE, CSn, Dual CSn and ALE with dual CSn
â Manual chip-enable (or use extra address pins)
â General Purpose
â Wide parallel interfaces for fast communications with CPLDs and FPGAs
â Data widths up to 32-bits
â Data rates up to 150 MB/second
â Optional âaddressâ sizes from 4 bits to 20 bits
â Optional clock output, read/write strobes, framing (with counter-based size), and clock-enable
input
â General parallel GPIO
â 1 to 32 bits, FIFOed with speed control
â Useful for custom peripherals or for digital data acquisition and actuator controls
EPI Block Diagram
Figure 10-1 on page 352 provides a block diagram of a Stellaris® EPI module.
June 29, 2010
351
Texas Instruments-Advance Information
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