LM3S9B81 Datasheet, PDF (501/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

Stellaris® LM3S9B81 Microcontroller
13.3.2.2
DMA Operation
The ADC module provides a request signal from each sample sequencer to the associated dedicated
channel of the μDMA controller. This configuration allows each sample sequencer to operate
independently and transfer data without processor intervention or reconfiguration. The ADC does
not support single transfer requests. A burst transfer request is asserted when the interrupt bit for
the sample sequence is set (IE bit in the ADCSSCTLn register is set).
The arbitration size of the μDMA transfer must be a power of 2, and the associated IE bits in the
ADDSSCTLn register must be set. For example, if the μDMA channel of SS0 has an arbitration
size of four, the IE3 bit (4th sample) and the IE7 bit (8th sample) must be set. Thus the μDMA
request occurs every time 4 samples have been acquired. No other special steps are needed to
enable the ADC module for μDMA operation.
Refer to the “Micro Direct Memory Access (μDMA)” on page 236 for more details about programming
the μDMA controller.
13.3.2.3
Prioritization
When sampling events (triggers) happen concurrently, they are prioritized for processing by the
values in the ADC Sample Sequencer Priority (ADCSSPRI) register. Valid priority values are in
the range of 0-3, with 0 being the highest priority and 3 being the lowest. Multiple active sample
sequencer units with the same priority do not provide consistent results, so software must ensure
that all active sample sequencer units have a unique priority value.
13.3.2.4
Sampling Events
Sample triggering for each sample sequencer is defined in the ADC Event Multiplexer Select
(ADCEMUX) register. Trigger sources include processor (default), analog comparators, an external
signal on GPIO PB4, a GP Timer, and continuous sampling. Software can initiate sampling by setting
the SSx bits in the ADC Processor Sample Sequence Initiate (ADCPSSI) register.
Care must be taken when using the continuous sampling trigger. If a sequencer's priority is too high,
it is possible to starve other lower priority sequencers.
13.3.2.5
Sample Phase Control
The trigger source for ADC0 and ADC1 may be independent or the two ADC units may operate
from the same trigger source and operate on the same or different inputs. If the converters are
running at the same sample rate, they may be configured to start the conversions coincidentally or
with one of 15 different discrete phases relative to each other. The sample time can be delayed
from the standard sampling time in 22.5° increments up to 337.5º using the ADC Sample Phase
Control (ADCSPC) register. Figure 13-3 on page 502 shows an example of various phase
relationships at a 1 Msps rate.
June 29, 2010
501
Texas Instruments-Advance Information