LM3S9B81 Datasheet, PDF (110/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

System Control
6.2.5.9
6.2.6
until the T_READY condition is met after one of the two changes above. It is the user's responsibility
to have a stable clock source (like the main oscillator) before the RCC/RCC2 register is switched
to use the PLL.
If the main PLL is enabled and the system clock is switched to use the PLL in one step, the system
control hardware continues to clock the microcontroller from the oscillator selected by the RCC/RCC2
register until the main PLL is stable (T_READY time met), after which it changes to the PLL. Software
can use many methods to ensure that the system is clocked from the main PLL, including periodically
polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register, and enabling the PLL Lock
interrupt.
The USB PLL is not protected during the lock time (T_READY), and software should ensure that the
USB PLL has locked before using the interface. Software can use many methods to ensure the
T_READY period has passed, including periodically polling the USBPLLLRIS bit in the Raw Interrupt
Status (RIS) register, and enabling the USB PLL Lock interrupt.
Main Oscillator Verification Circuit
The clock control includes circuitry to ensure that the main oscillator is running at the appropriate
frequency. The circuit monitors the main oscillator frequency and signals if the frequency is outside
of the allowable band of attached crystals.
The detection circuit is enabled using the CVAL bit in the Main Oscillator Control (MOSCCTL)
register. If this circuit is enabled and detects an error, the following sequence is performed by the
hardware:
1. The MOSCFAIL bit in the Reset Cause (RESC) register is set.
2. If the internal oscillator (PIOSC) is disabled, it is enabled.
3. The system clock is switched from the main oscillator to the PIOSC.
4. An internal power-on reset is initiated that lasts for 32 PIOSC periods.
5. Reset is de-asserted and the processor is directed to the NMI handler during the reset sequence.
System Control
For power-savings purposes, the RCGCn, SCGCn, and DCGCn registers control the clock gating
logic for each peripheral or block in the system while the microcontroller is in Run, Sleep, and
Deep-Sleep mode, respectively. The DC1 , DC2 and DC4 registers act as a write mask for the
RCGCn , SCGCn, and DCGCn registers.
There are three levels of operation for the microcontroller defined as:
■ Run Mode. In Run mode, the microcontroller actively executes code. Run mode provides normal
operation of the processor and all of the peripherals that are currently enabled by the RCGCn
registers. The system clock can be any of the available clock sources including the PLL.
■ Sleep Mode. In Sleep mode, the clock frequency of the active peripherals is unchanged, but the
processor and the memory subsystem are not clocked and therefore no longer execute code.
Sleep mode is entered by the Cortex-M3 core executing a WFI (Wait for Interrupt) instruction.
Any properly configured interrupt event in the system brings the processor back into Run mode.
See the system control NVIC section of the ARM® Cortex™-M3 Technical Reference Manual
for more details.
110
June 29, 2010
Texas Instruments-Advance Information