LM3S9B81 Datasheet, PDF (637/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

Stellaris® LM3S9B81 Microcontroller
function. The number in parentheses is the encoding that must be programmed into the PMCn field
in the GPIO Port Control (GPIOPCTL) register (page 336) to assign the SSI signal to the specified
GPIO port pin. For more information on configuring GPIOs, see “General-Purpose Input/Outputs
(GPIOs)” on page 294.
Table 15-1. Signals for SSI (100LQFP)
Pin Name
Pin Number Pin Mux / Pin Pin Type Buffer Type^a Description
Assignment
SSI0Clk
28
PA2 (1)
I/O
TTL
SSI module 0 clock.
SSI0Fss
29
PA3 (1)
I/O
TTL
SSI module 0 frame.
SSI0Rx
30
PA4 (1)
I
TTL
SSI module 0 receive.
SSI0Tx
31
PA5 (1)
O
TTL
SSI module 0 transmit.
SSI1Clk
60
PF2 (9)
I/O
74
PE0 (2)
76
PH4 (11)
TTL
SSI module 1 clock.
SSI1Fss
59
PF3 (9)
I/O
63
PH5 (11)
75
PE1 (2)
TTL
SSI module 1 frame.
SSI1Rx
42
PF4 (9)
I
62
PH6 (11)
95
PE2 (2)
TTL
SSI module 1 receive.
SSI1Tx
15
PH7 (11)
O
41
PF5 (9)
96
PE3 (2)
TTL
SSI module 1 transmit.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
Table 15-2. Signals for SSI (108BGA)
Pin Name
Pin Number Pin Mux / Pin Pin Type Buffer Type^a Description
Assignment
SSI0Clk
M4
PA2 (1)
I/O
TTL
SSI module 0 clock.
SSI0Fss
L4
PA3 (1)
I/O
TTL
SSI module 0 frame.
SSI0Rx
L5
PA4 (1)
I
TTL
SSI module 0 receive.
SSI0Tx
M5
PA5 (1)
O
TTL
SSI module 0 transmit.
SSI1Clk
J11
PF2 (9)
I/O
B11
PE0 (2)
B10
PH4 (11)
TTL
SSI module 1 clock.
SSI1Fss
J12
PF3 (9)
I/O
F10
PH5 (11)
A12
PE1 (2)
TTL
SSI module 1 frame.
SSI1Rx
K4
PF4 (9)
I
G3
PH6 (11)
A4
PE2 (2)
TTL
SSI module 1 receive.
SSI1Tx
H3
PH7 (11)
O
K3
PF5 (9)
B4
PE3 (2)
TTL
SSI module 1 transmit.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
15.3
Functional Description
The SSI performs serial-to-parallel conversion on data received from a peripheral device. The CPU
accesses data, control, and status information. The transmit and receive paths are buffered with
June 29, 2010
637
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