LM3S9B81 Datasheet, PDF (25/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

Stellaris® LM3S9B81 Microcontroller
Inter-Integrated Circuit Sound (I²S) Interface ............................................................................ 714
Register 1: I²S Transmit FIFO Data (I2STXFIFO), offset 0x000 .......................................................... 727
Register 2: I²S Transmit FIFO Configuration (I2STXFIFOCFG), offset 0x004 ...................................... 728
Register 3: I²S Transmit Module Configuration (I2STXCFG), offset 0x008 .......................................... 729
Register 4: I²S Transmit FIFO Limit (I2STXLIMIT), offset 0x00C ........................................................ 731
Register 5: I²S Transmit Interrupt Status and Mask (I2STXISM), offset 0x010 ..................................... 732
Register 6: I²S Transmit FIFO Level (I2STXLEV), offset 0x018 .......................................................... 733
Register 7: I²S Receive FIFO Data (I2SRXFIFO), offset 0x800 .......................................................... 734
Register 8: I²S Receive FIFO Configuration (I2SRXFIFOCFG), offset 0x804 ...................................... 735
Register 9: I²S Receive Module Configuration (I2SRXCFG), offset 0x808 ........................................... 736
Register 10: I²S Receive FIFO Limit (I2SRXLIMIT), offset 0x80C ......................................................... 739
Register 11: I²S Receive Interrupt Status and Mask (I2SRXISM), offset 0x810 ..................................... 740
Register 12: I²S Receive FIFO Level (I2SRXLEV), offset 0x818 ........................................................... 741
Register 13: I²S Module Configuration (I2SCFG), offset 0xC00 ............................................................ 742
Register 14: I²S Interrupt Mask (I2SIM), offset 0xC10 ......................................................................... 744
Register 15: I²S Raw Interrupt Status (I2SRIS), offset 0xC14 ............................................................... 746
Register 16: I²S Masked Interrupt Status (I2SMIS), offset 0xC18 ......................................................... 748
Register 17: I²S Interrupt Clear (I2SIC), offset 0xC1C ......................................................................... 750
Controller Area Network (CAN) Module ..................................................................................... 751
Register 1: CAN Control (CANCTL), offset 0x000 ............................................................................. 773
Register 2: CAN Status (CANSTS), offset 0x004 ............................................................................... 775
Register 3: CAN Error Counter (CANERR), offset 0x008 ................................................................... 778
Register 4: CAN Bit Timing (CANBIT), offset 0x00C .......................................................................... 779
Register 5: CAN Interrupt (CANINT), offset 0x010 ............................................................................. 781
Register 6: CAN Test (CANTST), offset 0x014 .................................................................................. 782
Register 7: CAN Baud Rate Prescaler Extension (CANBRPE), offset 0x018 ....................................... 784
Register 8: CAN IF1 Command Request (CANIF1CRQ), offset 0x020 ................................................ 785
Register 9: CAN IF2 Command Request (CANIF2CRQ), offset 0x080 ................................................ 785
Register 10: CAN IF1 Command Mask (CANIF1CMSK), offset 0x024 .................................................. 787
Register 11: CAN IF2 Command Mask (CANIF2CMSK), offset 0x084 .................................................. 787
Register 12: CAN IF1 Mask 1 (CANIF1MSK1), offset 0x028 ................................................................ 790
Register 13: CAN IF2 Mask 1 (CANIF2MSK1), offset 0x088 ................................................................ 790
Register 14: CAN IF1 Mask 2 (CANIF1MSK2), offset 0x02C ................................................................ 791
Register 15: CAN IF2 Mask 2 (CANIF2MSK2), offset 0x08C ................................................................ 791
Register 16: CAN IF1 Arbitration 1 (CANIF1ARB1), offset 0x030 ......................................................... 793
Register 17: CAN IF2 Arbitration 1 (CANIF2ARB1), offset 0x090 ......................................................... 793
Register 18: CAN IF1 Arbitration 2 (CANIF1ARB2), offset 0x034 ......................................................... 794
Register 19: CAN IF2 Arbitration 2 (CANIF2ARB2), offset 0x094 ......................................................... 794
Register 20: CAN IF1 Message Control (CANIF1MCTL), offset 0x038 .................................................. 796
Register 21: CAN IF2 Message Control (CANIF2MCTL), offset 0x098 .................................................. 796
Register 22: CAN IF1 Data A1 (CANIF1DA1), offset 0x03C ................................................................. 799
Register 23: CAN IF1 Data A2 (CANIF1DA2), offset 0x040 ................................................................. 799
Register 24: CAN IF1 Data B1 (CANIF1DB1), offset 0x044 ................................................................. 799
Register 25: CAN IF1 Data B2 (CANIF1DB2), offset 0x048 ................................................................. 799
Register 26: CAN IF2 Data A1 (CANIF2DA1), offset 0x09C ................................................................. 799
Register 27: CAN IF2 Data A2 (CANIF2DA2), offset 0x0A0 ................................................................. 799
Register 28: CAN IF2 Data B1 (CANIF2DB1), offset 0x0A4 ................................................................. 799
June 29, 2010
25
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