LM3S9B81 Datasheet, PDF (692/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

Inter-Integrated Circuit (I²C) Interface
Table 16-4. Inter-Integrated Circuit (I²C) Interface Register Map (continued)
Offset Name
I²C Slave
0x000 I2CSOAR
0x004 I2CSCSR
0x008 I2CSDR
0x00C I2CSIMR
0x010 I2CSRIS
0x014 I2CSMIS
0x018 I2CSICR
Type
Reset
Description
R/W
0x0000.0000 I2C Slave Own Address
RO
0x0000.0000 I2C Slave Control/Status
R/W
0x0000.0000 I2C Slave Data
R/W
0x0000.0000 I2C Slave Interrupt Mask
RO
0x0000.0000 I2C Slave Raw Interrupt Status
RO
0x0000.0000 I2C Slave Masked Interrupt Status
WO
0x0000.0000 I2C Slave Interrupt Clear
See
page
706
707
709
710
711
712
713
16.6
Register Descriptions (I²C Master)
The remainder of this section lists and describes the I²C master registers, in numerical order by
address offset. See also “Register Descriptions (I²C Slave)” on page 705.
692
June 29, 2010
Texas Instruments-Advance Information