LM3S9B81 Datasheet, PDF (12/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

Table of Contents
Figure 16-10. Master RECEIVE with Repeated START ............................................................. 687
Figure 16-11. Master RECEIVE with Repeated START after TRANSMIT with Repeated
START .............................................................................................................. 688
Figure 16-12. Master TRANSMIT with Repeated START after RECEIVE with Repeated
START .............................................................................................................. 689
Figure 16-13. Slave Command Sequence ................................................................................ 690
Figure 17-1. I²S Block Diagram ............................................................................................. 715
Figure 17-2. I²S Data Transfer ............................................................................................... 718
Figure 17-3. Left-Justified Data Transfer ................................................................................ 718
Figure 17-4. Right-Justified Data Transfer .............................................................................. 718
Figure 18-1. CAN Controller Block Diagram ............................................................................ 752
Figure 18-2. CAN Data/Remote Frame .................................................................................. 754
Figure 18-3. Message Objects in a FIFO Buffer ...................................................................... 762
Figure 18-4. CAN Bit Time .................................................................................................... 766
Figure 19-1. Ethernet Controller ............................................................................................. 805
Figure 19-2. Ethernet Controller Block Diagram ...................................................................... 805
Figure 19-3. Ethernet Frame ................................................................................................. 807
Figure 19-4. Interface to an Ethernet Jack .............................................................................. 814
Figure 20-1. USB Module Block Diagram ............................................................................... 864
Figure 21-1. Analog Comparator Module Block Diagram ....................................................... 1003
Figure 21-2. Structure of Comparator Unit ............................................................................ 1005
Figure 21-3. Comparator Internal Reference Structure .......................................................... 1005
Figure 22-1. 100-Pin LQFP Package Pin Diagram ................................................................ 1015
Figure 22-2. 108-Ball BGA Package Pin Diagram (Top View) ................................................. 1016
Figure 25-1. Load Conditions ............................................................................................... 1085
Figure 25-2. JTAG Test Clock Input Timing ........................................................................... 1087
Figure 25-3. JTAG Test Access Port (TAP) Timing ................................................................ 1088
Figure 25-4. External Reset Timing (RST) ............................................................................ 1088
Figure 25-5. Power-On Reset Timing ................................................................................... 1089
Figure 25-6. Brown-Out Reset Timing .................................................................................. 1089
Figure 25-7. Software Reset Timing ..................................................................................... 1089
Figure 25-8. Watchdog Reset Timing ................................................................................... 1089
Figure 25-9. MOSC Failure Reset Timing ............................................................................. 1090
Figure 25-10. SDRAM Initialization and Load Mode Register Timing ........................................ 1091
Figure 25-11. SDRAM Read Timing ....................................................................................... 1092
Figure 25-12. SDRAM Write Timing ....................................................................................... 1092
Figure 25-13. Host-Bus 8/16 Mode Read Timing ..................................................................... 1093
Figure 25-14. Host-Bus 8/16 Mode Write Timing ..................................................................... 1093
Figure 25-15. General-Purpose Mode Read and Write Timing ................................................. 1094
Figure 25-16. General-Purpose Mode iRDY Timing ................................................................. 1094
Figure 25-17. ADC Input Equivalency Diagram ....................................................................... 1096
Figure 25-18. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing
Measurement .................................................................................................. 1097
Figure 25-19. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............... 1097
Figure 25-20. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................... 1098
Figure 25-21. I²C Timing ....................................................................................................... 1098
Figure 25-22. I²S Master Mode Transmit Timing ..................................................................... 1099
Figure 25-23. I²S Master Mode Receive Timing ...................................................................... 1099
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June 29, 2010
Texas Instruments-Advance Information