LM3S9B81 Datasheet, PDF (585/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

Stellaris® LM3S9B81 Microcontroller
which means that the DIVINT field of the UARTIBRD register (see page 596) should be set to 10
decimal or 0xA. The value to be loaded into the UARTFBRD register (see page 597) is calculated
by the equation:
UARTFBRD[DIVFRAC] = integer(0.8507 * 64 + 0.5) = 54
With the BRD values in hand, the UART configuration is written to the module in the following order:
1. Disable the UART by clearing the UARTEN bit in the UARTCTL register.
2. Write the integer portion of the BRD to the UARTIBRD register.
3. Write the fractional portion of the BRD to the UARTFBRD register.
4. Write the desired serial parameters to the UARTLCRH register (in this case, a value of
0x0000.0060).
5. Optionally, configure the µDMA channel (see “Micro Direct Memory Access (μDMA)” on page 236)
and enable the DMA option(s) in the UARTDMACTL register.
6. Enable the UART by setting the UARTEN bit in the UARTCTL register.
14.5
Register Map
Table 14-4 on page 585 lists the UART registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that UART’s base address:
■ UART0: 0x4000.C000
■ UART1: 0x4000.D000
■ UART2: 0x4000.E000
Note that the UART module clock must be enabled before the registers can be programmed (see
page 174).
Note: The UART must be disabled (see the UARTEN bit in the UARTCTL register on page 600)
before any of the control registers are reprogrammed. When the UART is disabled during
a TX or RX operation, the current transaction is completed prior to the UART stopping.
Table 14-4. UART Register Map
Offset Name
Type
0x000 UARTDR
R/W
0x004 UARTRSR/UARTECR R/W
0x018 UARTFR
RO
0x020 UARTILPR
R/W
0x024 UARTIBRD
R/W
0x028 UARTFBRD
R/W
0x02C UARTLCRH
R/W
0x030 UARTCTL
R/W
0x034 UARTIFLS
R/W
Reset
0x0000.0000
0x0000.0000
0x0000.0090
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0300
0x0000.0012
Description
UART Data
UART Receive Status/Error Clear
UART Flag
UART IrDA Low-Power Register
UART Integer Baud-Rate Divisor
UART Fractional Baud-Rate Divisor
UART Line Control
UART Control
UART Interrupt FIFO Level Select
See
page
587
589
592
595
596
597
598
600
604
June 29, 2010
585
Texas Instruments-Advance Information