LM3S9B81 Datasheet, PDF (106/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

System Control
Figure 6-5. Main Clock Tree
XTAL^a
USBPWRDN^c
USB PLL
(240 MHz)
÷4
RXINT
RXFRAC
TXINT
TXFRAC
USEPWMDIV ^a
USB Clock
I²S Receive MCLK
I²S Transmit MCLK
MOSCDIS ^a
Main OSC
XTAL^a
PWRDN ^b
PLL
(400 MHz)
IOSCDIS^a
Precision
Internal OSC
(16 MHz)
Internal OSC
(30 kHz)
Hibernation
OSC
(32.768 kHz)
÷4
OSCSRC ^b,d
PWMDW ^a
PWM Clock
DIV400 ^c
÷2
USESYSDIV ^a,d
SYSDIV ^e
BYPASS ^b,d
PWRDN
System Clock
ADC Clock
÷ 25
a. Control provided by RCC register bit/field.
b. Control provided by RCC register bit/field or RCC2 register bit/field, if overridden with RCC2 register bit USERCC2.
c. Control provided by RCC2 register bit/field.
d. Also may be controlled by DSLPCLKCFG when in deep sleep mode.
e. Control provided by RCC register SYSDIV field, RCC2 register SYSDIV2 field if overridden with USERCC2 bit, or
[SYSDIV2,SYSDIV2LSB] if both USERCC2 and DIV400 bits are set.
Note: The figure above shows all features available on all Stellaris® Tempest-class microcontrollers.
In the RCC register, the SYSDIV field specifies which divisor is used to generate the system clock
from either the PLL output or the oscillator source (depending on how the BYPASS bit in this register
is configured). When using the PLL, the VCO frequency of 400 MHz is predivided by 2 before the
divisor is applied. Table 6-5 shows how the SYSDIV encoding affects the system clock frequency,
depending on whether the PLL is used (BYPASS=0) or another clock source is used (BYPASS=1).
The divisor is equivalent to the SYSDIV encoding plus 1. For a list of possible clock sources, see
Table 6-4 on page 104.
106
June 29, 2010
Texas Instruments-Advance Information