LM3S9B81 Datasheet, PDF (402/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

External Peripheral Interface (EPI)
Bit/Field
25:24
23:0
Name
CSCFG
reserved
Type
R/W
RO
Reset
0x0
Description
Chip Select Configuration
This field controls the chip select options, including an ALE format, a
single chip select, two chip selects, and an ALE combined with two chip
selects.
Value Description
0x0 ALE Configuration
EPI0S30 is used as an address latch (ALE). When using this
mode, the address and data should be muxed (HB16MODE field
in the EPIHB16CFG register should be configured to 0x0). If
needed, the address can be latched by external logic.
0x1 CSn Configuration
EPI0S30 is used as a Chip Select (CSn). When using this mode,
the address and data should not be muxed (HB816MODE field
in the EPIHB16CFG register should be configured to 0x1). In
this mode, the WR signal (EPI0S29) and the RD signal
(EPI0S28) are used to latch the address when CSn is low.
0x2 Dual CSn Configuration
EPI0S30 is used as CS0n and EPI0S27 is used as CS1n.
Whether CS0n or CS1n is asserted is determined by the most
significant address bit for a respective external address map.
This configuration can be used for a RAM bank split between
2 devices as well as when using both an external RAM and an
external peripheral.
0x3 ALE with Dual CSn Configuration
EPI0S30 is used as address latch (ALE), EPI0S27 is used as
CS1n, and EPI0S26 is used as CS0n. Whether CS0n or CS1n
is asserted is determined by the most significant address bit for
a respective external address map.
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
402
June 29, 2010
Texas Instruments-Advance Information