LM3S9B81 Datasheet, PDF (102/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

System Control
6.2.2.6
6.2.3
6.2.3.1
6.2.3.2
Watchdog Timer Reset
The Watchdog Timer module's function is to prevent system hangs. The LM3S9B81 microcontroller
has two Watchdog Timer modules in case one watchdog clock source fails. One watchdog is run
off the system clock and the other is run off the Precision Internal Oscillator (PIOSC). Each module
operates in the same manner except that because the PIOSC watchdog timer module is in a different
clock domain, register accesses must have a time delay between them. The watchdog timer can
be configured to generate an interrupt to the microcontroller on its first time-out and to generate a
reset on its second time-out.
After the watchdog's first time-out event, the 32-bit watchdog counter is reloaded with the value of
the Watchdog Timer Load (WDTLOAD) register and resumes counting down from that value. If
the timer counts down to zero again before the first time-out interrupt is cleared, and the reset signal
has been enabled, the watchdog timer asserts its reset signal to the microcontroller. The watchdog
timer reset sequence is as follows:
1. The watchdog timer times out for the second time without being serviced.
2. An internal reset is asserted.
3. The internal reset is released and the microcontroller loads from memory the initial stack pointer,
the initial program counter, and the first instruction designated by the program counter, and
then begins execution.
For more information on the Watchdog Timer module, see “Watchdog Timers” on page 471.
The watchdog reset timing is shown in Figure 25-8 on page 1089.
Non-Maskable Interrupt
The microcontroller has three sources of non-maskable interrupt (NMI):
■ The assertion of the NMI signal
■ A main oscillator verification error
■ The NMISET bit in the Interrupt Control and Status (ICSR) register in the Cortex-M3.
Software must check the cause of the interrupt in order to distinguish among the sources.
NMI Pin
The alternate function to GPIO port pin B7 is an NMI signal. The alternate function must be enabled
in the GPIO for the signal to be used as an interrupt, as described in “General-Purpose Input/Outputs
(GPIOs)” on page 294. Note that enabling the NMI alternate function requires the use of the GPIO
lock and commit function just like the GPIO port pins associated with JTAG/SWD functionality, see
page 332. The active sense of the NMI signal is High; asserting the enabled NMI signal above V_IH
initiates the NMI interrupt sequence.
Main Oscillator Verification Failure
The LM3S9B81 microcontroller provides a main oscillator verification circuit that generates an error
condition if the oscillator is running too fast or two slow. The main oscillator verification circuit can
be programmed to generate a reset event, at which time a Power-on Reset is generated and control
is transferred to the NMI handler. The NMI handler is used to address the main oscillator verification
failure because the necessary code can be removed from the general reset handler, speeding up
reset processing. The detection circuit is enabled by setting the CVAL bit in the Main Oscillator
102
June 29, 2010
Texas Instruments-Advance Information