LM3S9B81 Datasheet, PDF (329/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

Stellaris® LM3S9B81 Microcontroller
Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C
Note: Pins configured as digital inputs are Schmitt-triggered.
The GPIODEN register is the digital enable register. By default, all GPIO signals except those listed
below are configured out of reset to be undriven (tristate). Their digital function is disabled; they do
not drive a logic value on the pin and they do not allow the pin voltage into the GPIO receiver. To
use the pin as a digital input or output (either GPIO or alternate function), the corresponding GPIODEN
bit must be set.
Important: All GPIO pins are configured as GPIOs and tri-stated by default (GPIOAFSEL=0,
GPIODEN=0, GPIOPDR=0, GPIOPUR=0, and GPIOPCTL=0) with the exception of the
pins shown in the table below. A Power-On-Reset (POR) or asserting RST puts the pins
back to their default state.
Table 9-11. GPIO Pins With Non-Zero Reset Values
GPIO Pins
PA[1:0]
PA[5:2]
PB[3:2]
PC[3:0]
Default State
UART0
SSI0
I²C0
JTAG/SWD
GPIOAFSEL GPIODEN GPIOPDR GPIOPUR
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
GPIOPCTL
0x1
0x1
0x1
0x3
Note:
The GPIO commit control registers provide a layer of protection against accidental
programming of critical hardware peripherals. Protection is currently provided for the NMI
pin (PB7) and the four JTAG/SWD pins (PC[3:0]). Writes to protected bits of the GPIO
Alternate Function Select (GPIOAFSEL) register (see page 318), GPIO Pull Up Select
(GPIOPUR) register (see page 324), GPIO Pull-Down Select (GPIOPDR) register (see
page 326), and GPIO Digital Enable (GPIODEN) register (see page 329) are not committed
to storage unless the GPIO Lock (GPIOLOCK) register (see page 331) has been unlocked
and the appropriate bits of the GPIO Commit (GPIOCR) register (see page 332) have been
set.
June 29, 2010
329
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