LM3S9B81 Datasheet, PDF (391/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

Stellaris® LM3S9B81 Microcontroller
Bit/Field
23
22
21
20
19:16
15:8
Name
XFFEN
XFEEN
WRHIGH
RDHIGH
reserved
MAXWAIT
Type
R/W
R/W
R/W
R/W
RO
R/W
Reset
0
Description
External FIFO FULL Enable
Value Description
1 An external FIFO full signal can be used to control write cycles.
If this bit is set and the FFULL signal is high, XFIFO writes are
stalled.
0 No effect.
0
External FIFO EMPTY Enable
Value Description
1 An external FIFO empty signal can be used to control read
cycles. If this bit is set and the FEMPTY signal is high, XFIFO
reads are stalled.
0 No effect.
0
0
0x0
0x00
WRITE Strobe Polarity
Value Description
1 The WRITE strobe is WRn (active low).
0 The WRITE strobe is WR (active high).
If both CS0n and CS1n are enabled (the CSCFG field in the
EPIHB16CFG2 register is 0x2 or 0x3), the programmed write strobe
polarity is used for both CS0n and CS1n accesses.
READ Strobe Polarity
Value Description
1 The READ strobe is RDn (active low).
0 The READ strobe is RD (active high).
If both CS0n and CS1n are enabled (the CSCFG field in the
EPIHB16CFG2 register is 0x2 or 0x3), the programmed read strobe
polarity is used for both CS0n and CS1n accesses.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Maximum Wait
This field defines the maximum number of external clocks to wait while
an external FIFO ready signal is holding off a transaction (FFULL and
FEMPTY).
When this field is clear, the transaction is held off forever.
Note:
When the MODE field is configured to be 0x3 and the BLKEN
bit is set in the EPICFG register, enabling HB16 mode, this
field defaults to 0xFF.
June 29, 2010
391
Texas Instruments-Advance Information