LM3S9B81 Datasheet, PDF (22/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

Table of Contents
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 479
Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 480
Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 481
Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 482
Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 483
Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 484
Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 485
Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 486
Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 487
Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 488
Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 489
Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 490
Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 491
Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 492
Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 493
Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 494
Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 495
Analog-to-Digital Converter (ADC) ............................................................................................. 496
Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000 ............................................. 517
Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004 ........................................................... 518
Register 3: ADC Interrupt Mask (ADCIM), offset 0x008 ..................................................................... 520
Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C .................................................. 522
Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010 ............................................................ 525
Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014 ................................................. 527
Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018 ........................................................... 531
Register 8: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 ............................................. 532
Register 9: ADC Sample Phase Control (ADCSPC), offset 0x024 ...................................................... 534
Register 10: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 ................................. 535
Register 11: ADC Sample Averaging Control (ADCSAC), offset 0x030 ................................................. 537
Register 12: ADC Digital Comparator Interrupt Status and Clear (ADCDCISC), offset 0x034 ................. 538
Register 13: ADC Control (ADCCTL), offset 0x038 ............................................................................. 540
Register 14: ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 ............... 541
Register 15: ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 ........................................ 543
Register 16: ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 ................................ 546
Register 17: ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 ................................ 546
Register 18: ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 ................................ 546
Register 19: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ............................... 546
Register 20: ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C ............................. 547
Register 21: ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C ............................. 547
Register 22: ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C ............................ 547
Register 23: ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC ............................ 547
Register 24: ADC Sample Sequence 0 Operation (ADCSSOP0), offset 0x050 ...................................... 549
Register 25: ADC Sample Sequence 0 Digital Comparator Select (ADCSSDC0), offset 0x054 .............. 551
Register 26: ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 ............... 553
Register 27: ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 ............... 553
Register 28: ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 ........................................ 554
Register 29: ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 ........................................ 554
Register 30: ADC Sample Sequence 1 Operation (ADCSSOP1), offset 0x070 ...................................... 556
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June 29, 2010
Texas Instruments-Advance Information