LM3S9B81 Datasheet, PDF (82/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

Interrupts
4 Interrupts
The ARM Cortex-M3 processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and
handle all exceptions in Handler Mode. The processor state is automatically stored to the stack on
an exception and automatically restored from the stack at the end of the Interrupt Service Routine
(ISR). The vector is fetched in parallel to the state saving, enabling efficient interrupt entry. The
processor supports tail-chaining, which enables back-to-back interrupts to be performed without the
overhead of state saving and restoration.
Table 4-1 on page 82 lists all exception types. Software can set eight priority levels on seven of
these exceptions (system handlers) as well as on 47 interrupts (listed in Table 4-2 on page 83).
Priorities on the system handlers are set with the NVIC System Handler Priority registers. Interrupts
are enabled through the NVIC Interrupt Set Enable register and prioritized with the NVIC Interrupt
Priority registers. Priorities can be grouped by splitting priority levels into pre-emption priorities and
subpriorities. All of the interrupt registers are described in Chapter 8, “Nested Vectored Interrupt
Controller” in the ARM® Cortex™-M3 Technical Reference Manual.
Internally, the highest user-programmable priority (0) is treated as fourth priority, after a Reset,
Non-Maskable Interrupt (NMI), and a Hard Fault, in that order. Note that 0 is the default priority for
all the programmable priorities.
If you assign the same priority level to two or more interrupts, their hardware priority (the lower
position number) determines the order in which the processor activates them. For example, if both
GPIO Port A and GPIO Port B are priority level 1, then GPIO Port A has higher priority.
Important: It may take several processor cycles after a write to clear an interrupt source for the
NVIC to see the interrupt source de-assert. Thus if the interrupt clear is done as the
last action in an interrupt handler, it is possible for the interrupt handler to complete
while the NVIC sees the interrupt as still asserted, causing the interrupt handler to be
re-entered errantly. This situation can be avoided by either clearing the interrupt source
at the beginning of the interrupt handler or by performing a read or write after the write
to clear the interrupt source (and flush the write buffer).
See Chapter 5, “Exceptions” and Chapter 8, “Nested Vectored Interrupt Controller” in the ARM®
Cortex™-M3 Technical Reference Manual for more information on exceptions and interrupts.
Table 4-1. Exception Types
Exception Type
Vector
Number
Priority^a
Description
-
0
-
Stack top is loaded from the first entry of the vector table on reset.
Reset
1
-3 (highest) This exception is invoked on power up and warm reset. On the first
instruction, Reset drops to the lowest priority (and then is called the
base level of activation). This exception is asynchronous.
Non-Maskable
2
Interrupt (NMI)
-2
This exception is caused by the assertion of the NMI signal or by using
the NVIC Interrupt Control State register and cannot be stopped or
preempted by any exception but Reset. This exception is asynchronous.
Hard Fault
3
-1
This exception is caused by all classes of Fault, when the fault cannot
activate due to priority or the configurable fault handler has been
disabled. This exception is synchronous.
Memory
Management
4
programmable This exception is caused by an MPU mismatch, including access
violation and no match. This exception is synchronous.
82
June 29, 2010
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