LM3S9B81 Datasheet, PDF (10/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

Table of Contents
List of Figures
Figure 1-1. Stellaris^® LM3S9B81 Microcontroller High-Level Block Diagram ............................ 64
Figure 2-1. CPU Block Diagram ............................................................................................. 67
Figure 2-2. TPIU Block Diagram ............................................................................................ 75
Figure 5-1. JTAG Module Block Diagram ................................................................................ 86
Figure 5-2. Test Access Port State Machine ........................................................................... 89
Figure 5-3. IDCODE Register Format ..................................................................................... 95
Figure 5-4. BYPASS Register Format .................................................................................... 95
Figure 5-5. Boundary Scan Register Format ........................................................................... 96
Figure 6-1. Basic RST Configuration ...................................................................................... 99
Figure 6-2. External Circuitry to Extend Power-On Reset ....................................................... 100
Figure 6-3. Reset Circuit Controlled by Switch ...................................................................... 100
Figure 6-4. Power Architecture ............................................................................................ 103
Figure 6-5. Main Clock Tree ................................................................................................ 106
Figure 7-1. Internal Memory Block Diagram .......................................................................... 199
Figure 8-1. μDMA Block Diagram ......................................................................................... 237
Figure 8-2. Example of Ping-Pong μDMA Transaction ........................................................... 243
Figure 8-3. Memory Scatter-Gather, Setup and Configuration ................................................ 245
Figure 8-4. Memory Scatter-Gather, μDMA Copy Sequence .................................................. 246
Figure 8-5. Peripheral Scatter-Gather, Setup and Configuration ............................................. 248
Figure 8-6. Peripheral Scatter-Gather, μDMA Copy Sequence ............................................... 249
Figure 9-1. Digital I/O Pads ................................................................................................. 299
Figure 9-2. Analog/Digital I/O Pads ...................................................................................... 300
Figure 9-3. GPIODATA Write Example ................................................................................. 301
Figure 9-4. GPIODATA Read Example ................................................................................. 301
Figure 10-1. EPI Block Diagram ............................................................................................. 352
Figure 10-2. SDRAM Non-Blocking Read Cycle ...................................................................... 359
Figure 10-3. SDRAM Normal Read Cycle ............................................................................... 360
Figure 10-4. SDRAM Write Cycle ........................................................................................... 361
Figure 10-5. Host-Bus Read Cycle, MODE = 0x1, WRHIGH = 1, RDHIGH = 1 .......................... 368
Figure 10-6. Host-Bus Write Cycle, MODE = 0x1, WRHIGH = 1, RDHIGH = 1 .......................... 368
Figure 10-7. Host-Bus Write Cycle with Multiplexed Address and Data, MODE = 0x0, WRHIGH
= 1, RDHIGH = 1 ............................................................................................... 369
Figure 10-8. Continuous Read Mode Accesses ...................................................................... 369
Figure 10-9. Write Followed by Read to External FIFO ............................................................ 370
Figure 10-10. Two-Entry FIFO ................................................................................................. 370
Figure 10-11. Single-Cycle Write Access, FRM50=0, FRMCNT=0, WRCYC=0 ........................... 374
Figure 10-12. Two-Cycle Read, Write Accesses, FRM50=0, FRMCNT=0, RDCYC=1,
WRCYC=1 ........................................................................................................ 374
Figure 10-13. Read Accesses, FRM50=0, FRMCNT=0, RDCYC=1 ............................................ 375
Figure 10-14. FRAME Signal Operation, FRM50=0 and FRMCNT=0 ......................................... 375
Figure 10-15. FRAME Signal Operation, FRM50=0 and FRMCNT=1 ......................................... 375
Figure 10-16. FRAME Signal Operation, FRM50=0 and FRMCNT=2 ......................................... 376
Figure 10-17. FRAME Signal Operation, FRM50=1 and FRMCNT=0 ......................................... 376
Figure 10-18. FRAME Signal Operation, FRM50=1 and FRMCNT=1 ......................................... 376
Figure 10-19. FRAME Signal Operation, FRM50=1 and FRMCNT=2 ......................................... 376
Figure 10-20. iRDY Signal Operation, FRM50=0, FRMCNT=0, and RD2CYC=1 ......................... 377
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June 29, 2010
Texas Instruments-Advance Information