LM3S9B81 Datasheet, PDF (471/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

Stellaris® LM3S9B81 Microcontroller
12
Watchdog Timers
A watchdog timer can generate a nonmaskable interrupt (NMI) or a reset when a time-out value is
reached. The watchdog timer is used to regain control when a system has failed due to a software
error or due to the failure of an external device to respond in the expected way. The LM3S9B81
microcontroller has two Watchdog Timer Modules, one module is clocked by the system clock
(Watchdog Timer 0) and the other is clocked by the PIOSC (Watchdog Timer 1). The two modules
are identical except that WDT1 is in a different clock domain, and therefore requires synchronizers.
As a result, WDT1 has a bit defined in the Watchdog Timer Control (WDTCTL) register to indicate
when a write to a WDT1 register is complete. Software can use this bit to ensure that the previous
access has completed before starting the next access.
The Stellaris^® LM3S9B81 controller has two Watchdog Timer modules with the following features:
■ 32-bit down counter with a programmable load register
■ Separate watchdog clock with an enable
■ Programmable interrupt generation logic with interrupt masking
■ Lock register protection from runaway software
■ Reset generation logic with an enable/disable
■ User-enabled stalling when the microcontroller asserts the CPU Halt flag during debug
The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out,
and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured,
the lock register can be written to prevent the timer configuration from being inadvertently altered.
June 29, 2010
471
Texas Instruments-Advance Information