LM3S9B81 Datasheet, PDF (818/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

Ethernet Controller
Register 1: Ethernet MAC Raw Interrupt Status/Acknowledge
(MACRIS/MACIACK), offset 0x000
The MACRIS/MACIACK register is the interrupt status and acknowledge register. On a read, this
register gives the current status value of the corresponding interrupt prior to masking. On a write,
setting any bit clears the corresponding interrupt status bit.
Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK)
Base 0x4004.8000
Offset 0x000
Type R/W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
PHYINT MDINT RXER FOV TXEMP TXER RXINT
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RW1C RW1C RW1C RW1C RW1C RW1C RW1C
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:7
6
5
Name
reserved
PHYINT
MDINT
Type
Reset Description
RO 0x0000.00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
RW1C
0
PHY Interrupt
Value Description
1 An enabled interrupt in the PHY layer has occurred. MR29 in
the PHY must be read to determine the specific PHY event that
triggered this interrupt.
0 No interrupt.
This bit is cleared by writing a 1 to it.
RW1C
0
MII Transaction Complete
Value Description
1 A transaction (read or write) on the MII interface has completed
successfully.
0 No interrupt.
This bit is cleared by writing a 1 to it.
818
June 29, 2010
Texas Instruments-Advance Information