LM3S9B81 Datasheet, PDF (404/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

External Peripheral Interface (EPI)
Register 10: EPI Address Map (EPIADDRMAP), offset 0x01C
This register enables address mapping. The EPI controller can directly address memory and
peripherals. In addition, the EPI controller supports address mapping to allow indirect accesses in
the External RAM and External Peripheral areas.
If the external device is a peripheral, including a FIFO or a directly addressable device, the EPSZ
and EPADR bit fields should be configured for the address space. If the external device is SDRAM,
SRAM, or NOR Flash memory, the ERADR and ERSZ bit fields should be configured for the address
space.
If one of the Dual-Chip-Select modes is selected (CSCFG=0x2 or 0x3 in the EPIHBnCFG2 register),
both chip selects can share the peripheral or the memory space, or one chip select can use the
peripheral space and the other can use the memory space. If the EPADR field is not 0x0 and the
ERADR field is 0x0, then the address specified by EPADR is used for both chip selects, with CS0n
being asserted when the MSB of the address range is 0 and CS1n being asserted when the MSB
of the address range is 1. If the ERADR field is not 0x0 and the EPADR field is 0x0, then the address
specified by ERADR is used for both chip selects, with the MSB performing the same delineation. If
both the EPADR and the ERADR are not 0x0, then CS0n is asserted for the address range defined
by EPADR and CS1n is asserted for the address range defined by ERADR.
EPI Address Map (EPIADDRMAP)
Base 0x400D.0000
Offset 0x01C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
EPSZ
EPADR
ERSZ
ERADR
Type RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:8
7:6
Name
reserved
EPSZ
Type
RO
R/W
Reset Description
0x0000.00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0
External Peripheral Size
This field selects the size of the external peripheral. If the size of the
external peripheral is larger, a bus fault occurs. If the size of the external
peripheral is smaller, it wraps (upper address bits unused).
Note:
When not using byte selects in Host-Bus 16, data is accessed
on 2-byte boundaries. As a result, the available address space
is double the amount shown below.
Value Description
0x0 256 bytes; lower address range: 0x00 to 0xFF
0x1 64 KB; lower address range: 0x0000 to 0xFFFF
0x2 16 MB; lower address range: 0x00.0000 to 0xFF.FFFF
0x3 256 MB; lower address range: 0x000.0000 to 0xFFF.FFFF
404
June 29, 2010
Texas Instruments-Advance Information