LM3S9B81 Datasheet, PDF (24/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

Table of Contents
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 629
UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 630
UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 631
UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 632
UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 633
UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 634
Synchronous Serial Interface (SSI) ............................................................................................ 635
Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 650
Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 652
Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 654
Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 655
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 657
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 658
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 659
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 661
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 663
Register 10: SSI DMA Control (SSIDMACTL), offset 0x024 ................................................................. 664
Register 11: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 665
Register 12: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 666
Register 13: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 667
Register 14: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 668
Register 15: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 669
Register 16: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 670
Register 17: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 671
Register 18: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 672
Register 19: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 673
Register 20: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 674
Register 21: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 675
Register 22: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 676
Inter-Integrated Circuit (I²C) Interface ........................................................................................ 677
Register 1: I²C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 693
Register 2: I²C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 694
Register 3: I²C Master Data (I2CMDR), offset 0x008 ......................................................................... 699
Register 4: I²C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 700
Register 5: I²C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 701
Register 6: I²C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 702
Register 7: I²C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 703
Register 8: I²C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 704
Register 9: I²C Master Configuration (I2CMCR), offset 0x020 ............................................................ 705
Register 10: I²C Slave Own Address (I2CSOAR), offset 0x000 ............................................................ 706
Register 11: I²C Slave Control/Status (I2CSCSR), offset 0x004 ........................................................... 707
Register 12: I²C Slave Data (I2CSDR), offset 0x008 ........................................................................... 709
Register 13: I²C Slave Interrupt Mask (I2CSIMR), offset 0x00C ........................................................... 710
Register 14: I²C Slave Raw Interrupt Status (I2CSRIS), offset 0x010 ................................................... 711
Register 15: I²C Slave Masked Interrupt Status (I2CSMIS), offset 0x014 .............................................. 712
Register 16: I²C Slave Interrupt Clear (I2CSICR), offset 0x018 ............................................................ 713
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June 29, 2010
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