LM3S9B81 Datasheet, PDF (616/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

Universal Asynchronous Receivers/Transmitters (UARTs)
Bit/Field
4
3
2
1
0
Name
RXMIS
DSRMIS
DCDMIS
CTSMIS
RIMIS
Type
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
Description
UART Receive Masked Interrupt Status
Value Description
1 An unmasked interrupt was signaled due to passing through
the specified receive FIFO level.
0 An interrupt has not occurred or is masked.
This bit is cleared by writing a 1 to the RXIC bit in the UARTICR register.
UART Data Set Ready Modem Masked Interrupt Status
Value Description
1 An unmasked interrupt was signaled due to Data Set Ready.
0 An interrupt has not occurred or is masked.
This bit is cleared by writing a 1 to the DSRIC bit in the UARTICR
register.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
UART Data Carrier Detect Modem Masked Interrupt Status
Value Description
1 An unmasked interrupt was signaled due to Data Carrier Detect.
0 An interrupt has not occurred or is masked.
This bit is cleared by writing a 1 to the DCDIC bit in the UARTICR
register.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
UART Clear to Send Modem Masked Interrupt Status
Value Description
1 An unmasked interrupt was signaled due to Clear to Send.
0 An interrupt has not occurred or is masked.
This bit is cleared by writing a 1 to the CTSIC bit in the UARTICR
register.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
UART Ring Indicator Modem Masked Interrupt Status
Value Description
1 An unmasked interrupt was signaled due to Ring Indicator.
0 An interrupt has not occurred or is masked.
This bit is cleared by writing a 1 to the RIIC bit in the UARTICR register.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
616
June 29, 2010
Texas Instruments-Advance Information