LM3S9B81 Datasheet, PDF (718/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

Inter-Integrated Circuit Sound (I²S) Interface
Figure 17-2. I²S Data Transfer
SCK
Word Select
Serial Data
MSB
LSB MSB
WORD n-1
RIGHT
CHANNEL
WORD n
LEFT
CHANNEL
WORD n+1
RIGHT
CHANNEL
Figure 17-3. Left-Justified Data Transfer
Word
Select
SCLK
Serial
Data
System Data Size
Left Channel
MSB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LSB
Sample Size
Right Channel
MSB -1 -2 -3 -4 +5 +4 +3 +2 +1 LSB
Figure 17-4. Right-Justified Data Transfer
Word
Select
SCLK
Serial 0
Data
System Data Size
Left Channel
MSB -1 -2 -3 -4 -5
+7 +6 +5 +4 +3 +2 +1 LSB
Sample Size
Right Channel
MSB -1 -2 -3 -4 -5
+7 +6 +5 +4 +3 +2 +1 LSB
17.3.1
Transmit
The transmitter consists of a serial encoder, an 8-entry FIFO, and control logic. The transmitter has
independent MCLK (I2S0TXMCLK), SCLK (I2S0TXSCK), and Word-Select (I2S0TXWS) signals.
17.3.1.1
Serial Encoder
The serial encoder reads audio samples from the receive FIFO and converts them into an audio
stream. By configuring the serial encoder, common audio formats I²S, Left-Justified, and
Right-Justified are supported. The MSB is transmitted first. The sample size and system data size
are configurable with the SSZ and SDSZ bits in the I²S Transmit Module Configuration (I2STXCFG)
register. The sample size is the number of bits of data being transmitted, and the system data size
is the number of I2S0TXSCK transitions between the word select transitions. The system data size
must be large enough to accommodate the maximum sample size. In Mono mode, the sample data
718
June 29, 2010
Texas Instruments-Advance Information