LM3S9B81 Datasheet, PDF (435/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

Stellaris® LM3S9B81 Microcontroller
11.3.4
11.4
11.4.1
DMA Operation
The timers each have a dedicated μDMA channel and can provide a request signal to the μDMA
controller. The request is a burst type and occurs whenever a timer raw interrupt condition occurs.
The arbitration size of the μDMA transfer should be set to the amount of data that should be
transferred whenever a timer event occurs.
For example, to transfer 256 items, 8 items at a time every 10 ms, configure a timer to generate a
periodic timeout at 10 ms. Configure the μDMA transfer for a total of 256 items, with a burst size of
8 items. Each time the timer times out, the μDMA controller transfers 8 items, until all 256 items
have been transferred.
No other special steps are needed to enable Timers for μDMA operation. Refer to “Micro Direct
Memory Access (μDMA)” on page 236 for more details about programming the μDMA controller.
Initialization and Configuration
To use the general-purpose timers, the peripheral clock must be enabled by setting the TIMER0,
TIMER1, TIMER2, and TIMER3 bits in the RCGC1 register (see page 174). If using any CCP pins,
the clock to the appropriate GPIO module must be enabled via the RCGC2 register in the System
Control module (see page 183). To find out which GPIO port to enable, refer to Table 23-4 on page 1036.
Configure the PMCn fields in the GPIOPCTL register to assign the CCP signals to the appropriate
pins (see page 336 and Table 23-5 on page 1043).
This section shows module initialization and configuration examples for each of the supported timer
modes.
32-Bit One-Shot/Periodic Timer Mode
The GPTM is configured for 32-bit One-Shot and Periodic modes by the following sequence:
1. Ensure the timer is disabled (the TAEN bit in the GPTMCTL register is cleared) before making
any changes.
2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x0000.0000.
3. Configure the TAMR field in the GPTM Timer A Mode Register (GPTMTAMR):
a. Write a value of 0x1 for One-Shot mode.
b. Write a value of 0x2 for Periodic mode.
4. Optionally configure the TASNAPS, TAWOT, TAMTE, and TACDIR bits in the GPTMTAMR register
to select whether to capture the value of the free-running timer at time-out, use an external
trigger to start counting, configure an additional trigger or interrupt, and count up or down.
5. Load the start value into the GPTM Timer A Interval Load Register (GPTMTAILR).
6. If interrupts are required, set the appropriate bits in the GPTM Interrupt Mask Register
(GPTMIMR).
7. Set the TAEN bit in the GPTMCTL register to enable the timer and start counting.
8. Poll the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases,
the status flags are cleared by writing a 1 to the appropriate bit of the GPTM Interrupt Clear
Register (GPTMICR).
June 29, 2010
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Texas Instruments-Advance Information