LM3S9B81 Datasheet, PDF (407/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

Stellaris® LM3S9B81 Microcontroller
Register 13: EPI Read Address 0 (EPIRADDR0), offset 0x024
Register 14: EPI Read Address 1 (EPIRADDR1), offset 0x034
This register holds the current address value. When performing non-blocking reads via the
EPIRPSTDn registers, this register’s value forms the address (when used by the mode). That is,
when an EPIRPSTDn register is written with a non-0 value, this register is used as the first address.
After each read, it is incremented by the size specified by the corresponding EPIRSIZEn register.
Thus at the end of a read, this register contains the next address for the next read. For example, if
the last read was 0x20, and the size is word, then the register contains 0x24. When a non-blocking
read is cancelled, this register contains the next address that would have been read had it not been
cancelled. For example, if reading by bytes and 0x103 had been read but not 0x104, this register
contains 0x104. In this manner, the system can determine the number of values in the NBRFIFO
to drain.
Note that changing this register while a read is active has an unpredictable effect due to race
condition.
EPI Read Address 0 (EPIRADDR0)
Base 0x400D.0000
Offset 0x024
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
ADDR
Type RO
RO
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ADDR
Type R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:29
28:0
Name
reserved
ADDR
Type
Reset Description
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W 0x000.0000 Current Address
Next address to read.
June 29, 2010
407
Texas Instruments-Advance Information