LM3S9B81 Datasheet, PDF (366/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

External Peripheral Interface (EPI)
Table 10-6. EPI Host-Bus 16 Signal Connections (continued)
EPI Signal
CSCFG
BSEL
HB16 Signal (MODE
=ADMUX)
HB16 Signal (MODE
=ADNOMUX (Cont.
Read))
HB16 Signal
(MODE =XFIFO)
0
0x0
1
A27
BSEL1n
A11
BSEL1n
EPI0S27
0x1
0
1
A27
BSEL1n
A11
BSEL1n
FFULL
0x2
X
CS1n
CS1n
0x3
X
EPI0S28
X
X
RDn/OEn
RDn/OEn
RDn
EPI0S29
X
X
WRn
WRn
WRn
0x0
X
ALE
ALE
-
EPI0S30
0x1
X
0x2
X
CSn
CS0n
CSn
CS0n
CSn
CS0n
EPI0S31
0x3
X
X
X
ALE
Clock^d
ALE
Clock^d
-
Clock^d
a. "X" indicates the state of this field is a don't care.
b. In this mode, half-word accesses are used. AO is the LSB of the address and is equivalent to the system A1 address.
c. When an entry straddles several row, the signal configuration is the same for all rows.
d. The clock signal is not required for this mode and has unspecified timing relationships to other signals.
10.4.2.2
Speed of Transactions
The COUNT0 field in the EPIBAUD register must be configured to set the main transaction rate
based on what the slave device can support (including wiring considerations). The main control
transitions are normally ½ the baud rate (COUNT0 = 1) because the EPI block forces data vs. control
to change on alternating clocks. When using dual chip-selects, each chip select can access the bus
using differing baud rates by setting the CSBAUD bit in the EPIHBnCFG2 register. In this case, the
COUNT0 field controls the CS0n transactions, and the COUNT1 field controls the CS1n transactions.
Additionally, the Host-Bus mode provides read and write wait states for the data portion to support
different classes of device. These wait states stretch the data period (hold the rising edge of data
strobe) and may be used in all four sub-modes. The wait states are set using the WRWS and RDWS
bits in the EPI Host-Bus n Configuration (EPIHBnCFG) register.
10.4.2.3
Sub-Modes of Host Bus 8/16
The EPI controller supports four variants of the Host-Bus model using 8 or 16 bits of data in all four
cases. The four sub-modes are selected using the MODE bits in the EPIHBnCFG register, and are:
1. Address and data are muxed. This scheme is used by many 8051 devices, some Microchip PIC
parts, and some ATmega parts. When used for standard SRAMs, a latch must be used between
the microcontroller and the SRAM. This sub-mode is provided for compatibility with existing
devices that support data transfers without a latch (for example, LCD controllers or CPLDs). In
general, the de-muxed sub-mode should normally be used. The ALE configuration should be
used in this mode, as all Host-Bus accesses have an address phase followed by a data phase.
The ALE indicates to an external latch to capture the address then hold until the data phase.
The ALE configuration is controlled by configuring the CSCFG field to be 0x0 in the EPIHBnCFG2
register. The ALE can be enhanced to access two external devices with the addition of two
separate CSn signals. By configuring the CSCFG field in the to be 0x3 in the EPIHBnCFG2
366
June 29, 2010
Texas Instruments-Advance Information