LM3S9B81 Datasheet, PDF (86/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

JTAG Interface
5.1 Block Diagram
Figure 5-1. JTAG Module Block Diagram
TCK
TMS
TAP Controller
TDI
Instruction Register (IR)
BYPASS Data Register
Boundary Scan Data Register
IDCODE Data Register
ABORT Data Register
DPACC Data Register
APACC Data Register
TDO
Cortex-M3
Debug
Port
5.2 Signal Description
Table 5-1 on page 86 and Table 5-2 on page 87 list the external signals of the JTAG/SWD controller
and describe the function of each. The JTAG/SWD controller signals are alternate functions for
some GPIO signals, however note that the reset state of the pins is for the JTAG/SWD function.
The JTAG/SWD controller signals are under commit protection and require a special process to be
configured as GPIOs, see “Commit Control” on page 302. The column in the table below titled "Pin
Mux/Pin Assignment" lists the GPIO pin placement for the JTAG/SWD controller signals. The AFSEL
bit in the GPIO Alternate Function Select (GPIOAFSEL) register (page 318) is set to choose the
JTAG/SWD function.The number in parentheses is the encoding that must be programmed into the
PMCn field in the GPIO Port Control (GPIOPCTL) register (page 336) to assign the JTAG/SWD
controller signals to the specified GPIO port pin. For more information on configuring GPIOs, see
“General-Purpose Input/Outputs (GPIOs)” on page 294.
Table 5-1. Signals for JTAG_SWD_SWO (100LQFP)
Pin Name
SWCLK
SWDIO
SWO
TCK
TDI
TDO
Pin Number Pin Mux / Pin
Assignment
80
PC0 (3)
79
PC1 (3)
77
PC3 (3)
80
PC0 (3)
78
PC2 (3)
77
PC3 (3)
Pin Type
I
I/O
O
I
I
O
Buffer Type^a Description
TTL
JTAG/SWD CLK.
TTL
JTAG TMS and SWDIO.
TTL
JTAG TDO and SWO.
TTL
JTAG/SWD CLK.
TTL
JTAG TDI.
TTL
JTAG TDO and SWO.
86
June 29, 2010
Texas Instruments-Advance Information