LM3S9B81 Datasheet, PDF (69/1155 Pages) Texas Instruments – Stellaris® LM3S9B81 Microcontroller

Stellaris® LM3S9B81 Microcontroller
Table 2-1. 16-Bit Cortex-M3 Instruction Set Summary (continued)
Operation
Arithmetic shift right by number in register
Branch conditional
Branch unconditional
Bit clear
Software breakpoint
Branch with link
Branch with link and exchange
Branch and exchange
Compare not zero and branch
Compare zero and branch
Compare negation of register value with another register value
Compare immediate 8-bit value
Compare registers
Compare high register to low or high register
Change processor state
Copy high or low register value to another high or low register
Bitwise exclusive OR register values
Condition the following instruction
Condition the following two instructions
Condition the following three instructions
Condition the following four instructions
Multiple sequential memory word loads
Load memory word from base register address + 5-bit immediate offset
Load memory word from base register address + register offset
Load memory word from PC address + 8-bit immediate offset
Load memory word from SP address + 8-bit immediate offset
Load memory byte [7:0] from register address + 5-bit immediate offset
Load memory byte [7:0] from register address + register offset
Load memory halfword [15:0] from register address + 5-bit immediate offset
Load halfword [15:0] from register address + register offset
Load signed byte [7:0] from register address + register offset
Load signed halfword [15:0] from register address + register offset
Logical shift left by immediate number
Logical shift left by number in register
Logical shift right by immediate number
Logical shift right by number in register
Move immediate 8-bit value to register
Move low register value to low register
Move high or low register value to high or low register
Multiply register values
Move complement of register value to register
Negate register value and store in register
Assembler
ASR <Rd>, <Rs>
B<cond> <target address>
B <target_address>
BIC <Rd>, <Rm>
BKPT <immed_8>
BL <Rm>
BLX <Rm>
BX <Rm>
CBNZ <Rn>,<label>
CBZ <Rn>,<label>
CMN <Rn>, <Rm>
CMP <Rn>, #<immed_8>
CMP <Rn>, <Rm>
CMP <Rn>, <Rm>
CPS <effect>, <iflags>
CPY <Rd> <Rm>
EOR <Rd>, <Rm>
IT <cond>
IT<x> <cond>
IT<x><y> <cond>
IT<x><y><z> <cond>
LDMIA <Rn>!, <registers>
LDR <Rd>, [<Rn>, #<immed_5> * 4]
LDR <Rd>, [<Rn>, <Rm>]
LDR <Rd>, [PC, #<immed_8> * 4]
LDR, <Rd>, [SP, #<immed_8> * 4]
LDRB <Rd>, [<Rn>, #<immed_5>]
LDRB <Rd>, [<Rn>, <Rm>]
LDRH <Rd>, [<Rn>, #<immed_5> * 2]
LDRH <Rd>, [<Rn>, <Rm>]
LDRSB <Rd>, [<Rn>, <Rm>]
LDRSH <Rd>, [<Rn>, <Rm>]
LSL <Rd>, <Rm>, #<immed_5>
LSL <Rd>, <Rs>
LSR <Rd>, <Rm>, #<immed_5>
LSR <Rd>, <Rs>
MOV <Rd>, #<immed_8>
MOV <Rd>, <Rn>
MOV <Rd>, <Rm>
MUL <Rd>, <Rm>
MVN <Rd>, <Rm>
NEG <Rd>, <Rm>
June 29, 2010
69
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